Loading mm/Kconfig +1 −7 Original line number Diff line number Diff line Loading @@ -299,15 +299,9 @@ config BOUNCE # On the 'tile' arch, USB OHCI needs the bounce pool since tilegx will often # have more than 4GB of memory, but we don't currently use the IOTLB to present # a 32-bit address to OHCI. So we need to use a bounce pool instead. # # We also use the bounce pool to provide stable page writes for jbd. jbd # initiates buffer writeback without locking the page or setting PG_writeback, # and fixing that behavior (a second time; jbd2 doesn't have this problem) is # a major rework effort. Instead, use the bounce buffer to snapshot pages # (until jbd goes away). The only jbd user is ext3. config NEED_BOUNCE_POOL bool default y if (TILE && USB_OHCI_HCD) || (BLK_DEV_INTEGRITY && JBD) default y if TILE && USB_OHCI_HCD config NR_QUICK int Loading Loading
mm/Kconfig +1 −7 Original line number Diff line number Diff line Loading @@ -299,15 +299,9 @@ config BOUNCE # On the 'tile' arch, USB OHCI needs the bounce pool since tilegx will often # have more than 4GB of memory, but we don't currently use the IOTLB to present # a 32-bit address to OHCI. So we need to use a bounce pool instead. # # We also use the bounce pool to provide stable page writes for jbd. jbd # initiates buffer writeback without locking the page or setting PG_writeback, # and fixing that behavior (a second time; jbd2 doesn't have this problem) is # a major rework effort. Instead, use the bounce buffer to snapshot pages # (until jbd goes away). The only jbd user is ext3. config NEED_BOUNCE_POOL bool default y if (TILE && USB_OHCI_HCD) || (BLK_DEV_INTEGRITY && JBD) default y if TILE && USB_OHCI_HCD config NR_QUICK int Loading