Commit de990908 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-fixes-6.5-1' of... 

Merge tag 'irqchip-fixes-6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull irqchip fixes from Marc Zyngier:

  - Work around an erratum on GIC700, where a race between a CPU
    handling a wake-up interrupt, a change of affinity, and another
    CPU going to sleep can result in a lack of wake-up event on the
    next interrupt.

  - Fix the locking required on a VPE for GICv4

  - Enable Rockchip 3588001 erratum workaround for RK3588S

  - Fix the irq-bcm6345-l1 assumtions of the boot CPU always be
    the first CPU in the system

Link: https://lore.kernel.org/lkml/20230717113857.304919-1-maz@kernel.org
parents 67a4e1a3 6fe5c68e

Documentation/arm64/silicon-errata.rst

+3 −0
Original line number Diff line number Diff line
@@ -141,6 +141,9 @@ stable kernels. 
| ARM            | MMU-500         | #841119,826419  | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | GIC-700         | #2941627        | ARM64_ERRATUM_2941627       |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Broadcom       | Brahma-B53      | N/A             | ARM64_ERRATUM_845719        |

+----------------+-----------------+-----------------+-----------------------------+

| Broadcom       | Brahma-B53      | N/A             | ARM64_ERRATUM_843419        |

drivers/irqchip/irq-bcm6345-l1.c

+5 −9
Original line number Diff line number Diff line
@@ -82,6 +82,7 @@ struct bcm6345_l1_chip { 
};



struct bcm6345_l1_cpu {

	struct bcm6345_l1_chip	*intc;

	void __iomem		*map_base;

	unsigned int		parent_irq;

	u32			enable_cache[];
@@ -115,17 +116,11 @@ static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, 


static void bcm6345_l1_irq_handle(struct irq_desc *desc)

{

	struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc);

	struct bcm6345_l1_cpu *cpu;

	struct bcm6345_l1_cpu *cpu = irq_desc_get_handler_data(desc);

	struct bcm6345_l1_chip *intc = cpu->intc;

	struct irq_chip *chip = irq_desc_get_chip(desc);

	unsigned int idx;



#ifdef CONFIG_SMP

	cpu = intc->cpus[cpu_logical_map(smp_processor_id())];

#else

	cpu = intc->cpus[0];

#endif



	chained_irq_enter(chip, desc);



	for (idx = 0; idx < intc->n_words; idx++) {
@@ -253,6 +248,7 @@ static int __init bcm6345_l1_init_one(struct device_node *dn, 
	if (!cpu)

		return -ENOMEM;



	cpu->intc = intc;

	cpu->map_base = ioremap(res.start, sz);

	if (!cpu->map_base)

		return -ENOMEM;
@@ -271,7 +267,7 @@ static int __init bcm6345_l1_init_one(struct device_node *dn, 
		return -EINVAL;

	}

	irq_set_chained_handler_and_data(cpu->parent_irq,

						bcm6345_l1_irq_handle, intc);

						bcm6345_l1_irq_handle, cpu);



	return 0;

}

drivers/irqchip/irq-gic-v3-its.c

+48 −30
Original line number Diff line number Diff line
@@ -273,13 +273,23 @@ static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags) 
	raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);

}



static struct irq_chip its_vpe_irq_chip;



static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)

{

	struct its_vlpi_map *map = get_vlpi_map(d);

	struct its_vpe *vpe = NULL;

	int cpu;



	if (map) {

		cpu = vpe_to_cpuid_lock(map->vpe, flags);

	if (d->chip == &its_vpe_irq_chip) {

		vpe = irq_data_get_irq_chip_data(d);

	} else {

		struct its_vlpi_map *map = get_vlpi_map(d);

		if (map)

			vpe = map->vpe;

	}



	if (vpe) {

		cpu = vpe_to_cpuid_lock(vpe, flags);

	} else {

		/* Physical LPIs are already locked via the irq_desc lock */

		struct its_device *its_dev = irq_data_get_irq_chip_data(d);
@@ -293,10 +303,18 @@ static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags) 


static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)

{

	struct its_vlpi_map *map = get_vlpi_map(d);

	struct its_vpe *vpe = NULL;



	if (d->chip == &its_vpe_irq_chip) {

		vpe = irq_data_get_irq_chip_data(d);

	} else {

		struct its_vlpi_map *map = get_vlpi_map(d);

		if (map)

		vpe_to_cpuid_unlock(map->vpe, flags);

			vpe = map->vpe;

	}



	if (vpe)

		vpe_to_cpuid_unlock(vpe, flags);

}



static struct its_collection *valid_col(struct its_collection *col)
@@ -1433,14 +1451,29 @@ static void wait_for_syncr(void __iomem *rdbase) 
		cpu_relax();

}



static void direct_lpi_inv(struct irq_data *d)

static void __direct_lpi_inv(struct irq_data *d, u64 val)

{

	struct its_vlpi_map *map = get_vlpi_map(d);

	void __iomem *rdbase;

	unsigned long flags;

	u64 val;

	int cpu;



	/* Target the redistributor this LPI is currently routed to */

	cpu = irq_to_cpuid_lock(d, &flags);

	raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);



	rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;

	gic_write_lpir(val, rdbase + GICR_INVLPIR);

	wait_for_syncr(rdbase);



	raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);

	irq_to_cpuid_unlock(d, flags);

}



static void direct_lpi_inv(struct irq_data *d)

{

	struct its_vlpi_map *map = get_vlpi_map(d);

	u64 val;



	if (map) {

		struct its_device *its_dev = irq_data_get_irq_chip_data(d);
@@ -1453,15 +1486,7 @@ static void direct_lpi_inv(struct irq_data *d) 
		val = d->hwirq;

	}



	/* Target the redistributor this LPI is currently routed to */

	cpu = irq_to_cpuid_lock(d, &flags);

	raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);

	rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;

	gic_write_lpir(val, rdbase + GICR_INVLPIR);



	wait_for_syncr(rdbase);

	raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);

	irq_to_cpuid_unlock(d, flags);

	__direct_lpi_inv(d, val);

}



static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
@@ -3953,19 +3978,11 @@ static void its_vpe_send_inv(struct irq_data *d) 
{

	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);



	if (gic_rdists->has_direct_lpi) {

		void __iomem *rdbase;



		/* Target the redistributor this VPE is currently known on */

		raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);

		rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;

		gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR);

		wait_for_syncr(rdbase);

		raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);

	} else {

	if (gic_rdists->has_direct_lpi)

		__direct_lpi_inv(d, d->parent_data->hwirq);

	else

		its_vpe_send_cmd(vpe, its_send_inv);

}

}



static void its_vpe_mask_irq(struct irq_data *d)

{
@@ -4727,7 +4744,8 @@ static bool __maybe_unused its_enable_rk3588001(void *data) 
{

	struct its_node *its = data;



	if (!of_machine_is_compatible("rockchip,rk3588"))

	if (!of_machine_is_compatible("rockchip,rk3588") &&

	    !of_machine_is_compatible("rockchip,rk3588s"))

		return false;



	its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;

drivers/irqchip/irq-gic-v3.c

+61 −1
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ struct gic_chip_data { 
static void __iomem *t241_dist_base_alias[T241_CHIPS_MAX] __read_mostly;

static DEFINE_STATIC_KEY_FALSE(gic_nvidia_t241_erratum);



static DEFINE_STATIC_KEY_FALSE(gic_arm64_2941627_erratum);



static struct gic_chip_data gic_data __read_mostly;

static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
@@ -592,10 +594,39 @@ static void gic_irq_nmi_teardown(struct irq_data *d) 
	gic_irq_set_prio(d, GICD_INT_DEF_PRI);

}



static bool gic_arm64_erratum_2941627_needed(struct irq_data *d)

{

	enum gic_intid_range range;



	if (!static_branch_unlikely(&gic_arm64_2941627_erratum))

		return false;



	range = get_intid_range(d);



	/*

	 * The workaround is needed if the IRQ is an SPI and

	 * the target cpu is different from the one we are

	 * executing on.

	 */

	return (range == SPI_RANGE || range == ESPI_RANGE) &&

		!cpumask_test_cpu(raw_smp_processor_id(),

				  irq_data_get_effective_affinity_mask(d));

}



static void gic_eoi_irq(struct irq_data *d)

{

	write_gicreg(gic_irq(d), ICC_EOIR1_EL1);

	isb();



	if (gic_arm64_erratum_2941627_needed(d)) {

		/*

		 * Make sure the GIC stream deactivate packet

		 * issued by ICC_EOIR1_EL1 has completed before

		 * deactivating through GICD_IACTIVER.

		 */

		dsb(sy);

		gic_poke_irq(d, GICD_ICACTIVER);

	}

}



static void gic_eoimode1_eoi_irq(struct irq_data *d)
@@ -606,7 +637,11 @@ static void gic_eoimode1_eoi_irq(struct irq_data *d) 
	 */

	if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))

		return;



	if (!gic_arm64_erratum_2941627_needed(d))

		gic_write_dir(gic_irq(d));

	else

		gic_poke_irq(d, GICD_ICACTIVER);

}



static int gic_set_type(struct irq_data *d, unsigned int type)
@@ -1816,6 +1851,12 @@ static bool gic_enable_quirk_asr8601(void *data) 
	return true;

}



static bool gic_enable_quirk_arm64_2941627(void *data)

{

	static_branch_enable(&gic_arm64_2941627_erratum);

	return true;

}



static const struct gic_quirk gic_quirks[] = {

	{

		.desc	= "GICv3: Qualcomm MSM8996 broken firmware",
@@ -1863,6 +1904,25 @@ static const struct gic_quirk gic_quirks[] = { 
		.mask	= 0xffffffff,

		.init	= gic_enable_quirk_nvidia_t241,

	},

	{

		/*

		 * GIC-700: 2941627 workaround - IP variant [0,1]

		 *

		 */

		.desc	= "GICv3: ARM64 erratum 2941627",

		.iidr	= 0x0400043b,

		.mask	= 0xff0e0fff,

		.init	= gic_enable_quirk_arm64_2941627,

	},

	{

		/*

		 * GIC-700: 2941627 workaround - IP variant [2]

		 */

		.desc	= "GICv3: ARM64 erratum 2941627",

		.iidr	= 0x0402043b,

		.mask	= 0xff0f0fff,

		.init	= gic_enable_quirk_arm64_2941627,

	},

	{

	}

};