Commit de65ded4 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'socfpga_updates_for_3.15_v2' of... 

Merge tag 'socfpga_updates_for_3.15_v2' of git://git.rocketboards.org/linux-socfpga-next into next/drivers

Merge "SOCFPGA updates for 3.15 version 2" from Dinh Nguyen:

*Update SOCFPGA DTS to include ethernet, sd/mmc, and clock fixes
*Add stmmac ethernet glue layer
*Update socfpga_defconfig to include sd/mmc, and micrel_phy

* tag 'socfpga_updates_for_3.15_v2' of git://git.rocketboards.org/linux-socfpga-next

:
  dts: socfpga: Add sysmgr node so the gmac can use to reference
  dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
  dts: socfpga: Update clock entry to support multiple parents
  ARM: socfpga: Update socfpga_defconfig
  dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac.
  net: stmmac: Add SOCFPGA glue driver

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a929478f a5d6ac2a

Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt

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+23 −0
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* Altera SOCFPGA specific extensions to the Synopsys Designware Mobile

  Storage Host Controller



The Synopsys designware mobile storage host controller is used to interface

a SoC with storage medium such as eMMC or SD/MMC cards. This file documents

differences between the core Synopsys dw mshc controller properties described

by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific

extensions to the Synopsys Designware Mobile Storage Host Controller.



Required Properties:



* compatible: should be

	- "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform



Example:



	mmc: dwmmc0@ff704000 {

		compatible = "altr,socfpga-dw-mshc";

		reg = <0xff704000 0x1000>;

		interrupts = <0 129 4>;

		#address-cells = <1>;

		#size-cells = <0>;

	};

Documentation/devicetree/bindings/net/socfpga-dwmac.txt

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Altera SOCFPGA SoC DWMAC controller



The device node has following properties.



Required properties:

 - compatible	: Should contain "altr,socfpga-stmmac"

 - altr,sysmgr-syscon : Should be the phandle to the system manager node that

   encompasses the glue register, and the register offset.



Sub-nodes:

The dwmac core should be added as subnode to SOCFPGA dwmac glue.

- dwmac :	The binding details of dwmac can be found in

  Documentation/devicetree/bindings/net/stmmac.txt



Example:



ethernet0: ethernet0 {

	#address-cells = <1>;

	#size-cells = <1>;



	compatible = "altr,socfpga-stmmac";

	altr,sysmgr-syscon = <&sysmgr 0x60>;

	status = "disabled";

	ranges;



	gmac0: gmac0@ff700000 {

		compatible = "snps,dwmac-3.70a", "snps,dwmac";

		reg = <0xff700000 0x2000>;

		interrupts = <0 115 4>;

		interrupt-names = "macirq";

		mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */

		clocks = <&emac0_clk>;

		clock-names = "stmmaceth";

	};

};

arch/arm/boot/dts/socfpga.dtsi

+62 −25
Original line number Diff line number Diff line
@@ -92,7 +92,12 @@ 
					#address-cells = <1>;

					#size-cells = <0>;



					osc: osc1 {

					osc1: osc1 {

						#clock-cells = <0>;

						compatible = "fixed-clock";

					};



					osc2: osc2 {

						#clock-cells = <0>;

						compatible = "fixed-clock";

					};
@@ -100,7 +105,11 @@ 
					f2s_periph_ref_clk: f2s_periph_ref_clk {

						#clock-cells = <0>;

						compatible = "fixed-clock";

						clock-frequency = <10000000>;

					};



					f2s_sdram_ref_clk: f2s_sdram_ref_clk {

						#clock-cells = <0>;

						compatible = "fixed-clock";

					};



					main_pll: main_pll {
@@ -108,7 +117,7 @@ 
						#size-cells = <0>;

						#clock-cells = <0>;

						compatible = "altr,socfpga-pll-clock";

						clocks = <&osc>;

						clocks = <&osc1>;

						reg = <0x40>;



						mpuclk: mpuclk {
@@ -162,7 +171,7 @@ 
						#size-cells = <0>;

						#clock-cells = <0>;

						compatible = "altr,socfpga-pll-clock";

						clocks = <&osc>;

						clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;

						reg = <0x80>;



						emac0_clk: emac0_clk {
@@ -213,7 +222,7 @@ 
						#size-cells = <0>;

						#clock-cells = <0>;

						compatible = "altr,socfpga-pll-clock";

						clocks = <&osc>;

						clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;

						reg = <0xC0>;



						ddr_dqs_clk: ddr_dqs_clk {
@@ -441,26 +450,43 @@ 
				};

			};



		gmac0: ethernet@ff700000 {

			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";

		ethernet0: ethernet0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "altr,socfpga-stmmac";

			altr,sysmgr-syscon = <&sysmgr 0x60>;

			status = "disabled";

			ranges;



			gmac0: gmac0@ff700000 {

				compatible = "snps,dwmac-3.70a", "snps,dwmac";

				reg = <0xff700000 0x2000>;

				interrupts = <0 115 4>;

				interrupt-names = "macirq";

				mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */

				clocks = <&emac0_clk>;

				clock-names = "stmmaceth";

			status = "disabled";

			};

		};



		ethernet1: ethernet1 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "altr,socfpga-stmmac";

			altr,sysmgr-syscon = <&sysmgr 0x60>;

			status = "disabled";

			ranges;



		gmac1: ethernet@ff702000 {

			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";

			gmac1: gmac1@ff702000 {

				device_type = "network";

				compatible = "snps,dwmac-3.70a", "snps,dwmac";

				reg = <0xff702000 0x2000>;

				interrupts = <0 120 4>;

				interrupt-names = "macirq";

				mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */

				clocks = <&emac1_clk>;

				clock-names = "stmmaceth";

			status = "disabled";

			};

		};



		L2: l2-cache@fffef000 {
@@ -473,6 +499,17 @@ 
			arm,data-latency = <2 1 1>;

		};



		mmc: dwmmc0@ff704000 {

			compatible = "altr,socfpga-dw-mshc";

			reg = <0xff704000 0x1000>;

			interrupts = <0 139 4>;

			fifo-depth = <0x400>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&l4_mp_clk>, <&sdmmc_clk>;

			clock-names = "biu", "ciu";

		};



		/* Local timer */

		timer@fffec600 {

			compatible = "arm,cortex-a9-twd-timer";
@@ -526,8 +563,8 @@ 
			reg = <0xffd05000 0x1000>;

		};



		sysmgr@ffd08000 {

				compatible = "altr,sys-mgr";

		sysmgr: sysmgr@ffd08000 {

			compatible = "altr,sys-mgr", "syscon";

			reg = <0xffd08000 0x4000>;

		};

	};

arch/arm/boot/dts/socfpga_arria5.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -27,6 +27,17 @@ 
			};

		};



		dwmmc0@ff704000 {

			num-slots = <1>;

			supports-highspeed;

			broken-cd;



			slot@0 {

				reg = <0>;

				bus-width = <4>;

			};

		};



		serial0@ffc02000 {

			clock-frequency = <100000000>;

		};

arch/arm/boot/dts/socfpga_arria5_socdk.dts

+24 −0
Original line number Diff line number Diff line
@@ -37,4 +37,28 @@ 
		*/

		ethernet0 = &gmac1;

	};



	aliases {

		/* this allow the ethaddr uboot environmnet variable contents

		 * to be added to the gmac1 device tree blob.

		 */

		ethernet0 = &gmac1;

	};

};



&ethernet1 {

	status = "okay";

};



&gmac1 {

	phy-mode = "rgmii";



	rxd0-skew-ps = <0>;

	rxd1-skew-ps = <0>;

	rxd2-skew-ps = <0>;

	rxd3-skew-ps = <0>;

	txen-skew-ps = <0>;

	txc-skew-ps = <2600>;

	rxdv-skew-ps = <0>;

	rxc-skew-ps = <2000>;

};