Commit de612738 authored by Leo Chen's avatar Leo Chen Committed by Alex Deucher
Browse files

drm/amd/display: Exit idle optimizations before attempt to access PHY 



[Why & How]
DMUB may hang when powering down pixel clocks due to no dprefclk.

It is fixed by exiting idle optimization before the attempt to access PHY.

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarLeo Chen <sancchen@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4509e69a

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+3 −0
Original line number Diff line number Diff line
@@ -1792,10 +1792,13 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 
			hws->funcs.edp_backlight_control(edp_link_with_sink, false);

		}

		/*resume from S3, no vbios posting, no need to power down again*/

		clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);



		power_down_all_hw_blocks(dc);

		disable_vga_and_power_gate_all_controllers(dc);

		if (edp_link_with_sink && !keep_edp_vdd_on)

			dc->hwss.edp_power_control(edp_link_with_sink, false);

		clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);

	}

	bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);

}