Commit de46dbe4 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/edp: read sink MSO configuration for eDP 1.4+ 



Read and debug log the eDP sink MSO configuration. Do not actually do
anything with the information yet besides logging.

FIXME: The pixel overlap is present in DisplayID 2.0, but we don't have
parsing for that. Assume zero for now. We could also add quirks for
non-zero pixel overlap before DisplayID 2.0 parsing.

v3: Add placeholder for pixel overlap.

v2: Rename intel_dp_mso_init -> intel_edp_mso_init

Cc: Nischal Varide <nischal.varide@intel.com>
Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/24ef61574e5af12cd86d5b85afbfbd4ac2f9de25.1613054234.git.jani.nikula@intel.com
parent f8862617

drivers/gpu/drm/i915/display/intel_display_types.h

+2 −0
Original line number Diff line number Diff line
@@ -1493,6 +1493,8 @@ struct intel_dp { 
	int max_link_lane_count;

	/* Max rate for the current link */

	int max_link_rate;

	int mso_link_count;

	int mso_pixel_overlap;

	/* sink or branch descriptor */

	struct drm_dp_desc desc;

	struct drm_dp_aux aux;

drivers/gpu/drm/i915/display/intel_dp.c

+33 −0
Original line number Diff line number Diff line
@@ -3516,6 +3516,37 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) 
	}

}



static void intel_edp_mso_init(struct intel_dp *intel_dp)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	u8 mso;



	if (intel_dp->edp_dpcd[0] < DP_EDP_14)

		return;



	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {

		drm_err(&i915->drm, "Failed to read MSO cap\n");

		return;

	}



	/* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */

	mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;

	if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {

		drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);

		mso = 0;

	}



	if (mso) {

		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",

			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);

		drm_err(&i915->drm, "No source MSO support, disabling\n");

		mso = 0;

	}



	intel_dp->mso_link_count = mso;

	intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */

}



static bool

intel_edp_init_dpcd(struct intel_dp *intel_dp)

{
@@ -3599,6 +3630,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) 
	 */

	intel_edp_init_source_oui(intel_dp, true);



	intel_edp_mso_init(intel_dp);



	return true;

}