Commit de332bf2 authored by Liu Ying's avatar Liu Ying Committed by Shawn Guo
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clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks 



This patch adds SCU clocks support for i.MX8qxp DC0 subsystem bypass clocks.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: default avatarLiu Ying <victor.liu@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 95741fdb

drivers/clk/imx/clk-imx8qxp.c

+2 −0
Original line number Diff line number Diff line
@@ -119,6 +119,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) 
	clks[IMX_DC0_DISP1_CLK]		= imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);

	clks[IMX_DC0_PLL0_CLK]		= imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);

	clks[IMX_DC0_PLL1_CLK]		= imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);

	clks[IMX_DC0_BYPASS0_CLK]	= imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);

	clks[IMX_DC0_BYPASS1_CLK]	= imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);



	/* MIPI-LVDS SS */

	clks[IMX_MIPI0_I2C0_CLK]	= imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);

include/dt-bindings/clock/imx8-clock.h

+2 −0
Original line number Diff line number Diff line
@@ -64,6 +64,8 @@ 
#define IMX_DC0_PLL1_CLK				81

#define IMX_DC0_DISP0_CLK				82

#define IMX_DC0_DISP1_CLK				83

#define IMX_DC0_BYPASS0_CLK				84

#define IMX_DC0_BYPASS1_CLK				85



/* MIPI-LVDS SS */

#define IMX_MIPI_IPG_CLK				90