!851 perf/smmuv3: Enable HiSilicon Erratum quirk

Merge Pull Request from: @hejunhao3 
 
Some HiSilicon SMMU PMCG suffers the erratum that the global PMU disable
control sometimes fail to disable each used the counters. This will lead
to error or inaccurate data since before we enable the counters the
counter's still counting for the event used in last perf session.

This patch tries to fix this by hardening the global disable process.
Before disable the PMU, writing an invalid event type (0xff) to focibly
stop the counters. 
 
Link:https://gitee.com/openeuler/kernel/pulls/851

 

Reviewed-by: Yang Shen <shenyang39@huawei.com>
Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>