Commit de1c4296 authored by Kan Liang's avatar Kan Liang Committed by Aichun Shi
Browse files

perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids 

mainline inclusion
from mainline-v5.18-rc2
commit e590928d
category: feature
feature: SPR PMU core event enhancement
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I596BF



Intel-SIG: commit e590928d ("perf/x86/intel: Update the FRONTEND MSR
mask on Sapphire Rapids")

-------------------------------------

perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids

On Sapphire Rapids, the FRONTEND_RETIRED.MS_FLOWS event requires the
FRONTEND MSR value 0x8. However, the current FRONTEND MSR mask doesn't
support it.

Update intel_spr_extra_regs[] to support it.

Fixes: 61b985e3 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/1648482543-14923-2-git-send-email-kan.liang@linux.intel.com


Signed-off-by: default avatarYunying Sun <yunying.sun@intel.com>
Signed-off-by: default avatarJason Zeng <jason.zeng@intel.com>
Signed-off-by: default avatarAichun Shi <aichun.shi@intel.com>
parent 70b6f57f

arch/x86/events/intel/core.c

+1 −1
Original line number Diff line number Diff line
@@ -280,7 +280,7 @@ static struct extra_reg intel_spr_extra_regs[] __read_mostly = { 
	INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),

	INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),

	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),

	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),

	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),

	INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),

	INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),

	EVENT_EXTRA_END