+23
−1
Loading
Merge Pull Request from: @ci-robot PR sync from: Hongchen Zhang <zhanghongchen@loongson.cn> https://mailweb.openeuler.org/archives/list/kernel@openeuler.org/message/W6HCN4E264FRWJ4MYCVUWCUDVXEF2DQF/ Huacai Chen (1): LoongArch: Correct the cacheinfo sharing information Michal Schmidt (1): ice: fix unaligned access in ice_create_lag_recipe Ming Wang (1): rtc: loongson: clear TOY_MATCH0_REG in loongson_rtc_isr() Zhao Qunqin (3): LoongArch: Update the flush cache policy hda/pci: Add AZX_DCAPS_NO_TCSEL flag for Loongson HDA devices blutetooth/btusb: delay 1ms while suspending Hongchen Zhang (1): LoongArch: set CONFIG_CMA_SIZE_MBYTES to 0 https://gitee.com/openeuler/kernel/issues/IBQ4JL Link:https://gitee.com/openeuler/kernel/pulls/15271 Reviewed-by:Jason Zeng <jason.zeng@intel.com> Signed-off-by:
Zhang Peng <zhangpeng362@huawei.com>