Commit ddbefe7e authored by Michael Ellerman's avatar Michael Ellerman
Browse files

Merge branch 'topic/ppc-kvm' into next 

Merge the topic branch we're sharing with the kvm-ppc tree.
parents 3382a622 02ed21ae

arch/powerpc/include/asm/book3s/64/mmu-hash.h

+39 −8
Original line number Diff line number Diff line
@@ -70,7 +70,9 @@ 


#define HPTE_V_SSIZE_SHIFT	62

#define HPTE_V_AVPN_SHIFT	7

#define HPTE_V_COMMON_BITS	ASM_CONST(0x000fffffffffffff)

#define HPTE_V_AVPN		ASM_CONST(0x3fffffffffffff80)

#define HPTE_V_AVPN_3_0		ASM_CONST(0x000fffffffffff80)

#define HPTE_V_AVPN_VAL(x)	(((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)

#define HPTE_V_COMPARE(x,y)	(!(((x) ^ (y)) & 0xffffffffffffff80UL))

#define HPTE_V_BOLTED		ASM_CONST(0x0000000000000010)
@@ -80,14 +82,16 @@ 
#define HPTE_V_VALID		ASM_CONST(0x0000000000000001)



/*

 * ISA 3.0 have a different HPTE format.

 * ISA 3.0 has a different HPTE format.

 */

#define HPTE_R_3_0_SSIZE_SHIFT	58

#define HPTE_R_3_0_SSIZE_MASK	(3ull << HPTE_R_3_0_SSIZE_SHIFT)

#define HPTE_R_PP0		ASM_CONST(0x8000000000000000)

#define HPTE_R_TS		ASM_CONST(0x4000000000000000)

#define HPTE_R_KEY_HI		ASM_CONST(0x3000000000000000)

#define HPTE_R_RPN_SHIFT	12

#define HPTE_R_RPN		ASM_CONST(0x0ffffffffffff000)

#define HPTE_R_RPN_3_0		ASM_CONST(0x01fffffffffff000)

#define HPTE_R_PP		ASM_CONST(0x0000000000000003)

#define HPTE_R_PPP		ASM_CONST(0x8000000000000003)

#define HPTE_R_N		ASM_CONST(0x0000000000000004)
@@ -316,11 +320,42 @@ static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize, 
	 */

	v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);

	v <<= HPTE_V_AVPN_SHIFT;

	if (!cpu_has_feature(CPU_FTR_ARCH_300))

	v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;

	return v;

}



/*

 * ISA v3.0 defines a new HPTE format, which differs from the old

 * format in having smaller AVPN and ARPN fields, and the B field

 * in the second dword instead of the first.

 */

static inline unsigned long hpte_old_to_new_v(unsigned long v)

{

	/* trim AVPN, drop B */

	return v & HPTE_V_COMMON_BITS;

}



static inline unsigned long hpte_old_to_new_r(unsigned long v, unsigned long r)

{

	/* move B field from 1st to 2nd dword, trim ARPN */

	return (r & ~HPTE_R_3_0_SSIZE_MASK) |

		(((v) >> HPTE_V_SSIZE_SHIFT) << HPTE_R_3_0_SSIZE_SHIFT);

}



static inline unsigned long hpte_new_to_old_v(unsigned long v, unsigned long r)

{

	/* insert B field */

	return (v & HPTE_V_COMMON_BITS) |

		((r & HPTE_R_3_0_SSIZE_MASK) <<

		 (HPTE_V_SSIZE_SHIFT - HPTE_R_3_0_SSIZE_SHIFT));

}



static inline unsigned long hpte_new_to_old_r(unsigned long r)

{

	/* clear out B field */

	return r & ~HPTE_R_3_0_SSIZE_MASK;

}



/*

 * This function sets the AVPN and L fields of the HPTE  appropriately

 * using the base page size and actual page size.
@@ -341,12 +376,8 @@ static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize, 
 * aligned for the requested page size

 */

static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,

					  int actual_psize, int ssize)

					  int actual_psize)

{



	if (cpu_has_feature(CPU_FTR_ARCH_300))

		pa |= ((unsigned long) ssize) << HPTE_R_3_0_SSIZE_SHIFT;



	/* A 4K page needs no special encoding */

	if (actual_psize == MMU_PAGE_4K)

		return pa & HPTE_R_RPN;

arch/powerpc/include/asm/mmu.h

+5 −0
Original line number Diff line number Diff line
@@ -208,6 +208,11 @@ extern u64 ppc64_rma_size; 
/* Cleanup function used by kexec */

extern void mmu_cleanup_all(void);

extern void radix__mmu_cleanup_all(void);



/* Functions for creating and updating partition table on POWER9 */

extern void mmu_partition_table_init(void);

extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,

					  unsigned long dw1);

#endif /* CONFIG_PPC64 */



struct mm_struct;

arch/powerpc/include/asm/opal.h

+3 −0
Original line number Diff line number Diff line
@@ -220,9 +220,12 @@ int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id, 
int64_t opal_pci_poll2(uint64_t id, uint64_t data);



int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll);

int64_t opal_rm_int_get_xirr(__be32 *out_xirr, bool just_poll);

int64_t opal_int_set_cppr(uint8_t cppr);

int64_t opal_int_eoi(uint32_t xirr);

int64_t opal_rm_int_eoi(uint32_t xirr);

int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);

int64_t opal_rm_int_set_mfrr(uint32_t cpu, uint8_t mfrr);

int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,

			  uint32_t pe_num, uint32_t tce_size,

			  uint64_t dma_addr, uint32_t npages);

arch/powerpc/include/asm/reg.h

+15 −0
Original line number Diff line number Diff line
@@ -153,6 +153,8 @@ 
#define PSSCR_EC		0x00100000 /* Exit Criterion */

#define PSSCR_ESL		0x00200000 /* Enable State Loss */

#define PSSCR_SD		0x00400000 /* Status Disable */

#define PSSCR_PLS	0xf000000000000000 /* Power-saving Level Status */

#define PSSCR_GUEST_VIS	0xf0000000000003ff /* Guest-visible PSSCR fields */



/* Floating Point Status and Control Register (FPSCR) Fields */

#define FPSCR_FX	0x80000000	/* FPU exception summary */
@@ -236,6 +238,7 @@ 
#define SPRN_TEXASRU	0x83	/* ''	   ''	   ''	 Upper 32  */

#define   TEXASR_FS	__MASK(63-36) /* TEXASR Failure Summary */

#define SPRN_TFHAR	0x80	/* Transaction Failure Handler Addr */

#define SPRN_TIDR	144	/* Thread ID register */

#define SPRN_CTRLF	0x088

#define SPRN_CTRLT	0x098

#define   CTRL_CT	0xc0000000	/* current thread */
@@ -292,6 +295,7 @@ 
#define SPRN_HRMOR	0x139	/* Real mode offset register */

#define SPRN_HSRR0	0x13A	/* Hypervisor Save/Restore 0 */

#define SPRN_HSRR1	0x13B	/* Hypervisor Save/Restore 1 */

#define SPRN_ASDR	0x330	/* Access segment descriptor register */

#define SPRN_IC		0x350	/* Virtual Instruction Count */

#define SPRN_VTB	0x351	/* Virtual Time Base */

#define SPRN_LDBAR	0x352	/* LD Base Address Register */
@@ -302,6 +306,7 @@ 
#define SPRN_PMCR	0x374	/* Power Management Control Register */



/* HFSCR and FSCR bit numbers are the same */

#define FSCR_MSGP_LG	10	/* Enable MSGP */

#define FSCR_TAR_LG	8	/* Enable Target Address Register */

#define FSCR_EBB_LG	7	/* Enable Event Based Branching */

#define FSCR_TM_LG	5	/* Enable Transactional Memory */
@@ -315,6 +320,7 @@ 
#define   FSCR_EBB	__MASK(FSCR_EBB_LG)

#define   FSCR_DSCR	__MASK(FSCR_DSCR_LG)

#define SPRN_HFSCR	0xbe	/* HV=1 Facility Status & Control Register */

#define   HFSCR_MSGP	__MASK(FSCR_MSGP_LG)

#define   HFSCR_TAR	__MASK(FSCR_TAR_LG)

#define   HFSCR_EBB	__MASK(FSCR_EBB_LG)

#define   HFSCR_TM	__MASK(FSCR_TM_LG)
@@ -350,8 +356,10 @@ 
#define     LPCR_PECE0		ASM_CONST(0x0000000000004000)	/* ext. exceptions can cause exit */

#define     LPCR_PECE1		ASM_CONST(0x0000000000002000)	/* decrementer can cause exit */

#define     LPCR_PECE2		ASM_CONST(0x0000000000001000)	/* machine check etc can cause exit */

#define     LPCR_PECE_HVEE	ASM_CONST(0x0000400000000000)	/* P9 Wakeup on HV interrupts */

#define   LPCR_MER		ASM_CONST(0x0000000000000800)	/* Mediated External Exception */

#define   LPCR_MER_SH		11

#define	  LPCR_GTSE		ASM_CONST(0x0000000000000400)  	/* Guest Translation Shootdown Enable */

#define   LPCR_TC		ASM_CONST(0x0000000000000200)	/* Translation control */

#define   LPCR_LPES		0x0000000c

#define   LPCR_LPES0		ASM_CONST(0x0000000000000008)      /* LPAR Env selector 0 */
@@ -372,6 +380,12 @@ 
#define   PCR_VEC_DIS	(1ul << (63-0))	/* Vec. disable (bit NA since POWER8) */

#define   PCR_VSX_DIS	(1ul << (63-1))	/* VSX disable (bit NA since POWER8) */

#define   PCR_TM_DIS	(1ul << (63-2))	/* Trans. memory disable (POWER8) */

/*

 * These bits are used in the function kvmppc_set_arch_compat() to specify and

 * determine both the compatibility level which we want to emulate and the

 * compatibility level which the host is capable of emulating.

 */

#define   PCR_ARCH_207	0x8		/* Architecture 2.07 */

#define   PCR_ARCH_206	0x4		/* Architecture 2.06 */

#define   PCR_ARCH_205	0x2		/* Architecture 2.05 */

#define	SPRN_HEIR	0x153	/* Hypervisor Emulated Instruction Register */
@@ -1213,6 +1227,7 @@ 
#define PVR_ARCH_206	0x0f000003

#define PVR_ARCH_206p	0x0f100003

#define PVR_ARCH_207	0x0f000004

#define PVR_ARCH_300	0x0f000005



/* Macros for setting and retrieving special purpose registers */

#ifndef __ASSEMBLY__

arch/powerpc/kernel/cpu_setup_power.S

+1 −1
Original line number Diff line number Diff line
@@ -174,7 +174,7 @@ __init_FSCR: 
__init_HFSCR:

	mfspr	r3,SPRN_HFSCR

	ori	r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\

		      HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB

		      HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP

	mtspr	SPRN_HFSCR,r3

	blr