Commit dd627662 authored by David S. Miller's avatar David S. Miller
Browse files

Merge tag 'mlx5-fixes-2021-06-01' of git://git.kernel.org/pub/scm/linu 


x/kernel/git/saeed/linux

Saeed Mahameed says:

====================
mlx5 fixes 2021-06-01

This series introduces some fixes to mlx5 driver.
Please pull and let me know if there is any problem.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents b0003726 216214c6

drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c

+10 −2
Original line number Diff line number Diff line
@@ -1624,12 +1624,13 @@ static int mlx5e_set_fecparam(struct net_device *netdev, 
{

	struct mlx5e_priv *priv = netdev_priv(netdev);

	struct mlx5_core_dev *mdev = priv->mdev;

	unsigned long fec_bitmap;

	u16 fec_policy = 0;

	int mode;

	int err;



	if (bitmap_weight((unsigned long *)&fecparam->fec,

			  ETHTOOL_FEC_LLRS_BIT + 1) > 1)

	bitmap_from_arr32(&fec_bitmap, &fecparam->fec, sizeof(fecparam->fec) * BITS_PER_BYTE);

	if (bitmap_weight(&fec_bitmap, ETHTOOL_FEC_LLRS_BIT + 1) > 1)

		return -EOPNOTSUPP;



	for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
@@ -1893,6 +1894,13 @@ int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val 
	if (curr_val == new_val)

		return 0;



	if (new_val && !priv->profile->rx_ptp_support &&

	    priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {

		netdev_err(priv->netdev,

			   "Profile doesn't support enabling of CQE compression while hardware time-stamping is enabled.\n");

		return -EINVAL;

	}



	new_params = priv->channels.params;

	MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);

	if (priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE)

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+62 −15
Original line number Diff line number Diff line
@@ -3858,6 +3858,16 @@ static netdev_features_t mlx5e_fix_features(struct net_device *netdev, 
			netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");

	}



	if (mlx5e_is_uplink_rep(priv)) {

		features &= ~NETIF_F_HW_TLS_RX;

		if (netdev->features & NETIF_F_HW_TLS_RX)

			netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n");



		features &= ~NETIF_F_HW_TLS_TX;

		if (netdev->features & NETIF_F_HW_TLS_TX)

			netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n");

	}



	mutex_unlock(&priv->state_lock);



	return features;
@@ -3974,11 +3984,45 @@ int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx) 
	return mlx5e_ptp_rx_manage_fs(priv, set);

}



int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)

static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter)

{

	bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;

	int err;



	if (!rx_filter)

		/* Reset CQE compression to Admin default */

		return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def);



	if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))

		return 0;



	/* Disable CQE compression */

	netdev_warn(priv->netdev, "Disabling RX cqe compression\n");

	err = mlx5e_modify_rx_cqe_compression_locked(priv, false);

	if (err)

		netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);



	return err;

}



static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx)

{

	struct mlx5e_params new_params;



	if (ptp_rx == priv->channels.params.ptp_rx)

		return 0;



	new_params = priv->channels.params;

	new_params.ptp_rx = ptp_rx;

	return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,

					&new_params.ptp_rx, true);

}



int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)

{

	struct hwtstamp_config config;

	bool rx_cqe_compress_def;

	bool ptp_rx;

	int err;



	if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
@@ -3998,13 +4042,12 @@ int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) 
	}



	mutex_lock(&priv->state_lock);

	new_params = priv->channels.params;

	rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def;



	/* RX HW timestamp */

	switch (config.rx_filter) {

	case HWTSTAMP_FILTER_NONE:

		new_params.ptp_rx = false;

		ptp_rx = false;

		break;

	case HWTSTAMP_FILTER_ALL:

	case HWTSTAMP_FILTER_SOME:
@@ -4021,24 +4064,25 @@ int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) 
	case HWTSTAMP_FILTER_PTP_V2_SYNC:

	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:

	case HWTSTAMP_FILTER_NTP_ALL:

		new_params.ptp_rx = rx_cqe_compress_def;

		config.rx_filter = HWTSTAMP_FILTER_ALL;

		/* ptp_rx is set if both HW TS is set and CQE

		 * compression is set

		 */

		ptp_rx = rx_cqe_compress_def;

		break;

	default:

		mutex_unlock(&priv->state_lock);

		return -ERANGE;

		err = -ERANGE;

		goto err_unlock;

	}



	if (new_params.ptp_rx == priv->channels.params.ptp_rx)

		goto out;

	if (!priv->profile->rx_ptp_support)

		err = mlx5e_hwstamp_config_no_ptp_rx(priv,

						     config.rx_filter != HWTSTAMP_FILTER_NONE);

	else

		err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx);

	if (err)

		goto err_unlock;



	err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx,

				       &new_params.ptp_rx, true);

	if (err) {

		mutex_unlock(&priv->state_lock);

		return err;

	}

out:

	memcpy(&priv->tstamp, &config, sizeof(config));

	mutex_unlock(&priv->state_lock);
@@ -4047,6 +4091,9 @@ int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) 


	return copy_to_user(ifr->ifr_data, &config,

			    sizeof(config)) ? -EFAULT : 0;

err_unlock:

	mutex_unlock(&priv->state_lock);

	return err;

}



int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

+9 −0
Original line number Diff line number Diff line
@@ -2015,11 +2015,13 @@ static int __parse_cls_flower(struct mlx5e_priv *priv, 
				    misc_parameters_3);

	struct flow_rule *rule = flow_cls_offload_flow_rule(f);

	struct flow_dissector *dissector = rule->match.dissector;

	enum fs_flow_table_type fs_type;

	u16 addr_type = 0;

	u8 ip_proto = 0;

	u8 *match_level;

	int err;



	fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;

	match_level = outer_match_level;



	if (dissector->used_keys &
@@ -2145,6 +2147,13 @@ static int __parse_cls_flower(struct mlx5e_priv *priv, 
		if (match.mask->vlan_id ||

		    match.mask->vlan_priority ||

		    match.mask->vlan_tpid) {

			if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,

						     fs_type)) {

				NL_SET_ERR_MSG_MOD(extack,

						   "Matching on CVLAN is not supported");

				return -EOPNOTSUPP;

			}



			if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {

				MLX5_SET(fte_match_set_misc, misc_c,

					 outer_second_svlan_tag, 1);

drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c

+2 −1
Original line number Diff line number Diff line
@@ -219,6 +219,7 @@ esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, 
			 struct mlx5_fs_chains *chains,

			 int i)

{

	if (mlx5_chains_ignore_flow_level_supported(chains))

		flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;

	dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;

	dest[i].ft = mlx5_chains_get_tc_end_ft(chains);

drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c

+3 −0
Original line number Diff line number Diff line
@@ -349,6 +349,9 @@ static void mlx5_sync_reset_abort_event(struct work_struct *work) 
						      reset_abort_work);

	struct mlx5_core_dev *dev = fw_reset->dev;



	if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))

		return;



	mlx5_sync_reset_clear_reset_requested(dev, true);

	mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");

}