Unverified Commit dd5d787f authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'arm-soc/for-5.18/devicetree' of https://github.com/Broadcom/stblinux into arm/dt 

This pull request contains Broadcom ARM-based SoCs Device Tree changes
for 5.18, please pull the following:

- Arinc defines the switch ports of the RTL8365MB switch on the Asus
  RT-AC88U

- Richard provides cache information for the BCM2835/36/37 and BCM2711
  SoCs such that tools like "lscpu -C" can report it when supported

- Stefan adds support for the Raspberry Pi Zero 2 W (wireless)

- Matthew defines the MAC address NVMEM cells for the Cisco Meraki
  MX64/MX65 devices, he also fixes the LED for these platforms.

- Rafal adds the MAC addres NVMEM cell for the Luxul XWR-3150

* tag 'arm-soc/for-5.18/devicetree' of https://github.com/Broadcom/stblinux:
  ARM: dts: BCM5301X: Add Ethernet MAC address to Luxul XWR-3150
  ARM: dts: NSP: MX6X: correct LED function types
  ARM: dts: NSP: MX6X: get mac-address from eeprom
  arm64: dts: broadcom: Add reference to RPi Zero 2 W
  ARM: dts: Add Raspberry Pi Zero 2 W
  dt-bindings: arm: bcm2835: Add Raspberry Pi Zero 2 W
  ARM: dts: bcm2835/6: Add the missing L1/L2 cache information
  ARM: dts: bcm2711: Add the missing L1/L2 cache information
  ARM: dts: bcm2837: Add the missing L1/L2 cache information
  ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U

Link: https://lore.kernel.org/r/20220307194817.3754107-2-f.fainelli@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents e8f022f9 c8442f0f

Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ properties: 
              - raspberrypi,3-model-b-plus

              - raspberrypi,3-compute-module

              - raspberrypi,3-compute-module-lite

              - raspberrypi,model-zero-2-w

          - const: brcm,bcm2837



additionalProperties: true

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ 
	bcm2837-rpi-3-b.dtb \

	bcm2837-rpi-3-b-plus.dtb \

	bcm2837-rpi-cm3-io3.dtb \

	bcm2837-rpi-zero-2-w.dtb \

	bcm2711-rpi-400.dtb \

	bcm2711-rpi-4-b.dtb \

	bcm2711-rpi-cm4-io.dtb \

arch/arm/boot/dts/bcm2711.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -458,12 +458,26 @@ 
		#size-cells = <0>;

		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit



		/* Source for d/i-cache-line-size and d/i-cache-sets

		 * https://developer.arm.com/documentation/100095/0003

		 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en

		 * Source for d/i-cache-size

		 * https://www.raspberrypi.com/documentation/computers

		 * /processors.html#bcm2711

		 */

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a72";

			reg = <0>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x000000d8>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set

			next-level-cache = <&l2>;

		};



		cpu1: cpu@1 {
@@ -472,6 +486,13 @@ 
			reg = <1>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x000000e0>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set

			next-level-cache = <&l2>;

		};



		cpu2: cpu@2 {
@@ -480,6 +501,13 @@ 
			reg = <2>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x000000e8>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set

			next-level-cache = <&l2>;

		};



		cpu3: cpu@3 {
@@ -488,6 +516,28 @@ 
			reg = <3>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x000000f0>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set

			next-level-cache = <&l2>;

		};



		/* Source for d/i-cache-line-size and d/i-cache-sets

		 *  https://developer.arm.com/documentation/100095/0003

		 *  /Level-2-Memory-System/About-the-L2-memory-system?lang=en

		 *  Source for d/i-cache-size

		 *  https://www.raspberrypi.com/documentation/computers

		 *  /processors.html#bcm2711

		 */

		l2: l2-cache0 {

			compatible = "cache";

			cache-size = <0x100000>;

			cache-line-size = <64>;

			cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set

			cache-level = <2>;

		};

	};

arch/arm/boot/dts/bcm2835.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -14,6 +14,23 @@ 
			device_type = "cpu";

			compatible = "arm,arm1176jzf-s";

			reg = <0x0>;

			/* Source for d/i-cache-line-size and d/i-cache-sets

			 * https://developer.arm.com/documentation/ddi0301

			 * /h/level-one-memory-system/cache-organization?lang=en

			 *

			 * Source for d/i-cache-size

			 * https://forums.raspberrypi.com/viewtopic.php?t=98428

			 *

			 * NOTE: The BCM2835 has a L2 cache but it is dedicated to the GPU

			 * It can be shared with the CPU through fw settings,

			 * but this is not recommended.

			 */

			d-cache-size = <0x4000>;

			d-cache-line-size = <16>;

			d-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set

			i-cache-size = <0x4000>;

			i-cache-line-size = <16>;

			i-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set

		};

	};

arch/arm/boot/dts/bcm2836.dtsi

+50 −0
Original line number Diff line number Diff line
@@ -41,11 +41,26 @@ 
		#size-cells = <0>;

		enable-method = "brcm,bcm2836-smp";



		/* Source for d/i-cache-line-size and d/i-cache-sets

		 * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System

		 * /About-the-L1-memory-system?lang=en

		 *

		 * Source for d/i-cache-size

		 * https://forums.raspberrypi.com/viewtopic.php?t=98428

		 */



		v7_cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			reg = <0xf00>;

			clock-frequency = <800000000>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set

			i-cache-size = <0x8000>;

			i-cache-line-size = <32>;

			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set

			next-level-cache = <&l2>;

		};



		v7_cpu1: cpu@1 {
@@ -53,6 +68,13 @@ 
			compatible = "arm,cortex-a7";

			reg = <0xf01>;

			clock-frequency = <800000000>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set

			i-cache-size = <0x8000>;

			i-cache-line-size = <32>;

			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set

			next-level-cache = <&l2>;

		};



		v7_cpu2: cpu@2 {
@@ -60,6 +82,13 @@ 
			compatible = "arm,cortex-a7";

			reg = <0xf02>;

			clock-frequency = <800000000>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set

			i-cache-size = <0x8000>;

			i-cache-line-size = <32>;

			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set

			next-level-cache = <&l2>;

		};



		v7_cpu3: cpu@3 {
@@ -67,6 +96,27 @@ 
			compatible = "arm,cortex-a7";

			reg = <0xf03>;

			clock-frequency = <800000000>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set

			i-cache-size = <0x8000>;

			i-cache-line-size = <32>;

			i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set

			next-level-cache = <&l2>;

		};



		/* Source for cache-line-size + cache-sets

		 * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System

		 * /About-the-L2-Memory-system?lang=en

		 * Source for cache-size

		 * https://forums.raspberrypi.com/viewtopic.php?t=98428

		 */

		l2: l2-cache0 {

			compatible = "cache";

			cache-size = <0x80000>;

			cache-line-size = <64>;

			cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set

			cache-level = <2>;

		};

	};

};