Commit dd422a6f authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/host-xgene' into next 

* pci/host-xgene:
  PCI: xgene: Clean up whitespace
  PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset
  PCI: xgene: Fix platform_get_irq() error handling
parents e9e256df fca4848b

drivers/pci/host/pci-xgene-msi.c

+1 −1
Original line number Diff line number Diff line
@@ -489,7 +489,7 @@ static int xgene_msi_probe(struct platform_device *pdev) 
		if (virt_msir < 0) {

			dev_err(&pdev->dev, "Cannot translate IRQ index %d\n",

				irq_index);

			rc = -EINVAL;

			rc = virt_msir;

			goto error;

		}

		xgene_msi->msi_groups[irq_index].gic_irq = virt_msir;

drivers/pci/host/pci-xgene.c

+20 −21
Original line number Diff line number Diff line
@@ -61,7 +61,7 @@ 
#define SZ_1T				(SZ_1G*1024ULL)

#define PIPE_PHY_RATE_RD(src)		((0xc000 & (u32)(src)) >> 0xe)



#define ROOT_CAP_AND_CTRL		0x5C

#define XGENE_V1_PCI_EXP_CAP		0x40



/* PCIe IP version */

#define XGENE_PCIE_IP_VER_UNKN		0
@@ -189,7 +189,7 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, 
	 * Avoid this by not claiming to support CRS.

	 */

	if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&

	    ((where & ~0x3) == ROOT_CAP_AND_CTRL))

	    ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))

		*val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);



	if (size <= 2)
@@ -593,8 +593,7 @@ static void xgene_pcie_clear_config(struct xgene_pcie_port *port) 
		xgene_pcie_writel(port, i, 0);

}



static int xgene_pcie_setup(struct xgene_pcie_port *port,

			    struct list_head *res,

static int xgene_pcie_setup(struct xgene_pcie_port *port, struct list_head *res,

			    resource_size_t io_base)

{

	struct device *dev = port->dev;