Commit dd37fba9 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Do DIO FIFO enable after DP video stream enable 



[Why]
Avoids a race condition where DIO FIFO can underflow due to no incoming
data available.

[How]
Shift the FIFO enable below stream enable.

Make sure fullness level is written before the DIO reset takes place
and that we're not doing it twice.

Reviewed-by: default avatarSyed Hassan <Syed.Hassan@amd.com>
Acked-by: default avatarJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b6d1c39b

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c

+8 −5
Original line number Diff line number Diff line
@@ -56,7 +56,8 @@ static void enc314_enable_fifo(struct stream_encoder *enc) 


	/* TODO: Confirm if we need to wait for DIG_SYMCLK_FE_ON */

	REG_WAIT(DIG_FE_CNTL, DIG_SYMCLK_FE_ON, 1, 10, 5000);

	REG_UPDATE_2(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1, DIG_FIFO_READ_START_LEVEL, 0x7);

	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);

	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);

	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 1, 10, 5000);

	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);

	REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, 0, 10, 5000);
@@ -316,15 +317,11 @@ static void enc314_stream_encoder_dp_unblank( 
	/* switch DP encoder to CRTC data, but reset it the fifo first. It may happen

	 * that it overflows during mode transition, and sometimes doesn't recover.

	 */

	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);

	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);

	udelay(10);



	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);



	/* DIG Resync FIFO now needs to be explicitly enabled. */

	enc314_enable_fifo(enc);



	/* wait 100us for DIG/DP logic to prime

	 * (i.e. a few video lines)

	 */
@@ -340,6 +337,12 @@ static void enc314_stream_encoder_dp_unblank( 


	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);



	/*

	 * DIG Resync FIFO now needs to be explicitly enabled.

	 * This should come after DP_VID_STREAM_ENABLE per HW docs.

	 */

	enc314_enable_fifo(enc);



	dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);

}