Unverified Commit dd23e953 authored by Conor Dooley's avatar Conor Dooley Committed by Palmer Dabbelt
Browse files

RISC-V: replace cbom instructions with an insn-def 

Using the cbom instructions directly in ALT_CMO_OP, requires toolchain
support for the instructions. Using an insn-def will allow for removal
of toolchain version checks in the build system & simplification of the
proposed [1] function-based CMO scheme.

Link: https://lore.kernel.org/linux-riscv/fb3b34ae-e35e-4dc2-a8f4-19984a2f58a8@app.fastmail.com/

 [1]
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20230108163356.3063839-3-conor@kernel.org


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 6067c3aa

arch/riscv/include/asm/errata_list.h

+2 −1
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include <asm/alternative.h>

#include <asm/csr.h>

#include <asm/insn-def.h>

#include <asm/vendorid_list.h>



#ifdef CONFIG_ERRATA_SIFIVE
@@ -125,7 +126,7 @@ asm volatile(ALTERNATIVE_2( \ 
	"mv a0, %1\n\t"							\

	"j 2f\n\t"							\

	"3:\n\t"							\

	"cbo." __stringify(_op) " (a0)\n\t"				\

	CBO_##_op(a0)							\

	"add a0, a0, %0\n\t"						\

	"2:\n\t"							\

	"bltu a0, %2, 3b\n\t"						\

arch/riscv/include/asm/insn-def.h

+12 −0
Original line number Diff line number Diff line
@@ -180,4 +180,16 @@ 
	INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(51),		\

	       __RD(0), RS1(gaddr), RS2(vmid))



#define CBO_inval(base)						\

	INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),		\

	       RS1(base), SIMM12(0))



#define CBO_clean(base)						\

	INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),		\

	       RS1(base), SIMM12(1))



#define CBO_flush(base)						\

	INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),		\

	       RS1(base), SIMM12(2))



#endif /* __ASM_INSN_DEF_H */