Commit dd123dd0 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r9a07g054: Add MTU3a node 



Add MTU3a node to R9A07G054 (RZ/V2L) SoC DTSI.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230417090159.191346-2-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 26336d66

arch/arm64/boot/dts/renesas/r9a07g054.dtsi

+70 −0
Original line number Diff line number Diff line
@@ -174,6 +174,76 @@ 
		#size-cells = <2>;

		ranges;



		mtu3: timer@10001200 {

			compatible = "renesas,r9a07g054-mtu3",

				     "renesas,rz-mtu3";

			reg = <0 0x10001200 0 0xb00>;

			interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",

					  "tgiv0", "tgie0", "tgif0",

					  "tgia1", "tgib1", "tgiv1", "tgiu1",

					  "tgia2", "tgib2", "tgiv2", "tgiu2",

					  "tgia3", "tgib3", "tgic3", "tgid3",

					  "tgiv3",

					  "tgia4", "tgib4", "tgic4", "tgid4",

					  "tgiv4",

					  "tgiu5", "tgiv5", "tgiw5",

					  "tgia6", "tgib6", "tgic6", "tgid6",

					  "tgiv6",

					  "tgia7", "tgib7", "tgic7", "tgid7",

					  "tgiv7",

					  "tgia8", "tgib8", "tgic8", "tgid8",

					  "tgiv8", "tgiu8";

			clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;

			power-domains = <&cpg>;

			resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;

			#pwm-cells = <2>;

			status = "disabled";

		};



		ssi0: ssi@10049c00 {

			compatible = "renesas,r9a07g054-ssi",

				     "renesas,rz-ssi";