Commit dd03aeef authored by Mark Zhang's avatar Mark Zhang Committed by Thierry Reding
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arm64: tegra: Add support for NVIDIA Shield TV 



Add initial device-tree support for NVIDIA Shield TV (a.k.a. Darcy)
based upon Tegra210 SoC with 3 GiB of LPDDR4 RAM.

Signed-off-by: default avatarMark Zhang <markz@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 968ebd84

arch/arm64/boot/dts/nvidia/Makefile

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@@ -4,5 +4,6 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb 
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb

dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb

dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb

dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb

dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb

dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb

arch/arm64/boot/dts/nvidia/tegra210-p2894-0050-a08.dts

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// SPDX-License-Identifier: GPL-2.0

/dts-v1/;



#include "tegra210-p2894.dtsi"



/ {

	model = "NVIDIA Shield TV";

	compatible = "nvidia,p2894-0050-a08", "nvidia,darcy", "nvidia,tegra210";

};

arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi

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// SPDX-License-Identifier: GPL-2.0



#include "tegra210.dtsi"



/ {

	aliases {

		serial0 = &uarta;

	};



	chosen {

		bootargs = "earlycon";

		stdout-path = "serial0:115200n8";

	};



	memory {

		device_type = "memory";

		reg = <0x0 0x80000000 0x0 0xc0000000>;

	};



	serial@70006000 {

		status = "okay";

	};



	pmc@7000e400 {

		nvidia,invert-interrupt;

		nvidia,suspend-mode = <0>;

		nvidia,cpu-pwr-good-time = <0>;

		nvidia,cpu-pwr-off-time = <0>;

		nvidia,core-pwr-good-time = <4587 3876>;

		nvidia,core-pwr-off-time = <39065>;

		nvidia,core-power-req-active-high;

		nvidia,sys-clock-req-active-high;

		status = "okay";

	};



	sdhci@700b0600 {

		bus-width = <8>;

		non-removable;

		status = "okay";

	};



	clocks {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;



		clk32k_in: clock@0 {

			compatible = "fixed-clock";

			reg = <0>;

			#clock-cells = <0>;

			clock-frequency = <32768>;

		};

	};



	cpus {

		cpu@0 {

			enable-method = "psci";

		};



		cpu@1 {

			enable-method = "psci";

		};



		cpu@2 {

			enable-method = "psci";

		};



		cpu@3 {

			enable-method = "psci";

		};

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};

};