Commit dcea1a81 authored by Tan, Tee Min's avatar Tan, Tee Min Committed by Jakub Kicinski
Browse files

stmmac: intel: Update PCH PTP clock rate from 200MHz to 204.8MHz 



Current Intel platform has an output of ~976ms interval
when probed on 1 Pulse-per-Second(PPS) hardware pin.

The correct PTP clock frequency for PCH GbE should be 204.8MHz
instead of 200MHz. PSE GbE PTP clock rate remains at 200MHz.

Fixes: 58da0cfa ("net: stmmac: create dwmac-intel.c to contain all Intel platform")
Signed-off-by: default avatarLing Pei Lee <pei.lee.ling@intel.com>
Signed-off-by: default avatarTan, Tee Min <tee.min.tan@intel.com>
Signed-off-by: default avatarVoon Weifeng <weifeng.voon@intel.com>
Signed-off-by: default avatarGan Yi Fang <yi.fang.gan@intel.com>
Link: https://lore.kernel.org/r/20221108020811.12919-1-yi.fang.gan@intel.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent d75aed14

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c

+9 −2
Original line number Diff line number Diff line
@@ -629,7 +629,6 @@ static int ehl_common_data(struct pci_dev *pdev, 
{

	plat->rx_queues_to_use = 8;

	plat->tx_queues_to_use = 8;

	plat->clk_ptp_rate = 200000000;

	plat->use_phy_wol = 1;



	plat->safety_feat_cfg->tsoee = 1;
@@ -654,6 +653,8 @@ static int ehl_sgmii_data(struct pci_dev *pdev, 
	plat->serdes_powerup = intel_serdes_powerup;

	plat->serdes_powerdown = intel_serdes_powerdown;



	plat->clk_ptp_rate = 204800000;



	return ehl_common_data(pdev, plat);

}
@@ -667,6 +668,8 @@ static int ehl_rgmii_data(struct pci_dev *pdev, 
	plat->bus_id = 1;

	plat->phy_interface = PHY_INTERFACE_MODE_RGMII;



	plat->clk_ptp_rate = 204800000;



	return ehl_common_data(pdev, plat);

}
@@ -683,6 +686,8 @@ static int ehl_pse0_common_data(struct pci_dev *pdev, 
	plat->bus_id = 2;

	plat->addr64 = 32;



	plat->clk_ptp_rate = 200000000;



	intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);



	return ehl_common_data(pdev, plat);
@@ -722,6 +727,8 @@ static int ehl_pse1_common_data(struct pci_dev *pdev, 
	plat->bus_id = 3;

	plat->addr64 = 32;



	plat->clk_ptp_rate = 200000000;



	intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);



	return ehl_common_data(pdev, plat);
@@ -757,7 +764,7 @@ static int tgl_common_data(struct pci_dev *pdev, 
{

	plat->rx_queues_to_use = 6;

	plat->tx_queues_to_use = 4;

	plat->clk_ptp_rate = 200000000;

	plat->clk_ptp_rate = 204800000;

	plat->speed_mode_2500 = intel_speed_mode_2500;



	plat->safety_feat_cfg->tsoee = 1;