Commit dcda94c9 authored by Larry Finger's avatar Larry Finger Committed by Greg Kroah-Hartman
Browse files

staging: r8188eu: Replace BITn with BIT(n) 



The driver uses BITn instead of BIT(n). All such usage is converted.

Note that this patch does not address any warnings that checkpatch
will find. These include missing space around operators and lines
that are too long. These problems will be addressed in a separate
patch.

Acked-by: default avatarPhillip Potter <phil@philpotter.co.uk>
Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Link: https://lore.kernel.org/r/20210810180511.8986-1-Larry.Finger@lwfinger.net


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 987219ad

drivers/staging/r8188eu/core/rtw_ioctl_set.c

+1 −1
Original line number Diff line number Diff line
@@ -564,7 +564,7 @@ u8 rtw_set_802_11_add_key(struct adapter *padapter, struct ndis_802_11_key *key) 


		bgroup = false;

	} else {

		/*  Group key - KeyIndex(BIT30 == 0) */

		/*  Group key - KeyIndex(BIT(30) == 0) */

		/*  when add wep key through add key and didn't assigned encryption type before */

		if ((padapter->securitypriv.ndisauthtype <= 3) &&

		    (padapter->securitypriv.dot118021XGrpPrivacy == 0)) {

drivers/staging/r8188eu/hal/HalPhyRf_8188e.c

+20 −20
Original line number Diff line number Diff line
@@ -336,11 +336,11 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E( 
						ODM_SetBBReg(dm_odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32);



						value32 = ((X * ele_D)>>7)&0x01;

						ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT28, value32);

						ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT(28), value32);

					} else {

						ODM_SetBBReg(dm_odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u8)OFDM_index[1]]);

						ODM_SetBBReg(dm_odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);

						ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT28, 0x00);

						ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT(28), 0x00);

					}

				}

			}
@@ -392,7 +392,7 @@ phy_PathA_IQK_8188E(struct adapter *adapt, bool configPathB) 
	regE94 = ODM_GetBBReg(dm_odm, rTx_Power_Before_IQK_A, bMaskDWord);

	regE9C = ODM_GetBBReg(dm_odm, rTx_Power_After_IQK_A, bMaskDWord);



	if (!(regeac & BIT28) &&

	if (!(regeac & BIT(28)) &&

	    (((regE94 & 0x03FF0000)>>16) != 0x142) &&

	    (((regE9C & 0x03FF0000)>>16) != 0x42))

		result |= 0x01;
@@ -446,7 +446,7 @@ phy_PathA_RxIQK(struct adapter *adapt, bool configPathB) 
	regE94 = ODM_GetBBReg(dm_odm, rTx_Power_Before_IQK_A, bMaskDWord);

	regE9C = ODM_GetBBReg(dm_odm, rTx_Power_After_IQK_A, bMaskDWord);



	if (!(regeac & BIT28) &&

	if (!(regeac & BIT(28)) &&

	    (((regE94 & 0x03FF0000)>>16) != 0x142) &&

	    (((regE9C & 0x03FF0000)>>16) != 0x42))

		result |= 0x01;
@@ -495,7 +495,7 @@ phy_PathA_RxIQK(struct adapter *adapt, bool configPathB) 
	ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);

	ODM_SetRFReg(dm_odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180);



	if (!(regeac & BIT27) &&		/* if Tx is OK, check whether Rx is OK */

	if (!(regeac & BIT(27)) &&		/* if Tx is OK, check whether Rx is OK */

	    (((regEA4 & 0x03FF0000)>>16) != 0x132) &&

	    (((regeac & 0x03FF0000)>>16) != 0x36))

		result |= 0x02;
@@ -525,14 +525,14 @@ phy_PathB_IQK_8188E(struct adapter *adapt) 
	regec4 = ODM_GetBBReg(dm_odm, rRx_Power_Before_IQK_B_2, bMaskDWord);

	regecc = ODM_GetBBReg(dm_odm, rRx_Power_After_IQK_B_2, bMaskDWord);



	if (!(regeac & BIT31) &&

	if (!(regeac & BIT(31)) &&

	    (((regeb4 & 0x03FF0000)>>16) != 0x142) &&

	    (((regebc & 0x03FF0000)>>16) != 0x42))

		result |= 0x01;

	else

		return result;



	if (!(regeac & BIT30) &&

	if (!(regeac & BIT(30)) &&

	    (((regec4 & 0x03FF0000)>>16) != 0x132) &&

	    (((regecc & 0x03FF0000)>>16) != 0x36))

		result |= 0x02;
@@ -732,9 +732,9 @@ _PHY_MACSettingCalibration( 
	ODM_Write1Byte(dm_odm, MACReg[i], 0x3F);



	for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) {

		ODM_Write1Byte(dm_odm, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));

		ODM_Write1Byte(dm_odm, MACReg[i], (u8)(MACBackup[i]&(~BIT(3))));

	}

	ODM_Write1Byte(dm_odm, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));

	ODM_Write1Byte(dm_odm, MACReg[i], (u8)(MACBackup[i]&(~BIT(5))));

}



void
@@ -907,15 +907,15 @@ static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t, 
	}



	/* BB setting */

	ODM_SetBBReg(dm_odm, rFPGA0_RFMOD, BIT24, 0x00);

	ODM_SetBBReg(dm_odm, rFPGA0_RFMOD, BIT(24), 0x00);

	ODM_SetBBReg(dm_odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);

	ODM_SetBBReg(dm_odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);

	ODM_SetBBReg(dm_odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);



	ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);

	ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);

	ODM_SetBBReg(dm_odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);

	ODM_SetBBReg(dm_odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);

	ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01);

	ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01);

	ODM_SetBBReg(dm_odm, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00);

	ODM_SetBBReg(dm_odm, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00);



	if (is2t) {

		ODM_SetBBReg(dm_odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);
@@ -1255,21 +1255,21 @@ static void phy_setrfpathswitch_8188e(struct adapter *adapt, bool main, bool is2 


	if (!adapt->hw_init_completed) {

		u8 u1btmp;

		u1btmp = ODM_Read1Byte(dm_odm, REG_LEDCFG2) | BIT7;

		u1btmp = ODM_Read1Byte(dm_odm, REG_LEDCFG2) | BIT(7);

		ODM_Write1Byte(dm_odm, REG_LEDCFG2, u1btmp);

		ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFParameter, BIT13, 0x01);

		ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFParameter, BIT(13), 0x01);

	}



	if (is2t) {	/* 92C */

		if (main)

			ODM_SetBBReg(dm_odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1);	/* 92C_Path_A */

			ODM_SetBBReg(dm_odm, rFPGA0_XB_RFInterfaceOE, BIT(5)|BIT(6), 0x1);	/* 92C_Path_A */

		else

			ODM_SetBBReg(dm_odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2);	/* BT */

			ODM_SetBBReg(dm_odm, rFPGA0_XB_RFInterfaceOE, BIT(5)|BIT(6), 0x2);	/* BT */

	} else {			/* 88C */

		if (main)

			ODM_SetBBReg(dm_odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2);	/* Main */

			ODM_SetBBReg(dm_odm, rFPGA0_XA_RFInterfaceOE, BIT(8)|BIT(9), 0x2);	/* Main */

		else

			ODM_SetBBReg(dm_odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1);	/* Aux */

			ODM_SetBBReg(dm_odm, rFPGA0_XA_RFInterfaceOE, BIT(8)|BIT(9), 0x1);	/* Aux */

	}

}

drivers/staging/r8188eu/hal/odm.c

+34 −34
Original line number Diff line number Diff line
@@ -426,7 +426,7 @@ void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value) 


void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm)

{

	pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT9);

	pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT(9));

	pDM_Odm->RFPathRxEnable = (u8) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);

	if (pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))

		pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
@@ -798,8 +798,8 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 


	if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {

		/* hold ofdm counter */

		ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */

		ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */

		ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */

		ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */



		ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);

		FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
@@ -824,8 +824,8 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 
		}



		/* hold cck counter */

		ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1);

		ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1);

		ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);

		ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);



		ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);

		FalseAlmCnt->Cnt_Cck_fail = ret_value;
@@ -847,20 +847,20 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 


		if (pDM_Odm->SupportICType >= ODM_RTL8723A) {

			/* reset false alarm counter registers */

			ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1);

			ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0);

			ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1);

			ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0);

			ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);

			ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);

			ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);

			ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);

			/* update ofdm counter */

			ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /* update page C counter */

			ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /* update page D counter */

			ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0); /* update page C counter */

			ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0); /* update page D counter */



			/* reset CCK CCA counter */

			ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0);

			ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2);

			ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(13)|BIT(12), 0);

			ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(13)|BIT(12), 2);

			/* reset CCK FA counter */

			ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0);

			ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2);

			ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(15)|BIT(14), 0);

			ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(15)|BIT(14), 2);

		}

	} else { /* FOR ODM_IC_11AC_SERIES */

		/* read OFDM FA counter */
@@ -869,11 +869,11 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 
		FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail;



		/*  reset OFDM FA coutner */

		ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1);

		ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0);

		ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 1);

		ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 0);

		/*  reset CCK FA counter */

		ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0);

		ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1);

		ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 0);

		ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 1);

	}

}
@@ -1000,7 +1000,7 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 
	}

	if (pDM_PSTable->initialize == 0) {

		pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;

		pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;

		pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT(3))>>3;

		pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;

		pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;

		pDM_PSTable->initialize = 1;
@@ -1031,23 +1031,23 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 
			/*  <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. */

			/*  Suggested by SD3 Yu-Nan. 2011.01.20. */

			if (pDM_Odm->SupportICType == ODM_RTL8723A)

				ODM_SetBBReg(pDM_Odm, 0x874, BIT5, 0x1); /* Reg874[5]=1b'1 */

				ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x1); /* Reg874[5]=1b'1 */

			ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */

			ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */

			ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */

			ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */

			ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */

			ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */

			ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */

			ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */

			ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */

			ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */

		} else {

			ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->Reg874);

			ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);

			ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), pDM_PSTable->RegC70);

			ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);

			ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);

			ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);

			ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0);



			if (pDM_Odm->SupportICType == ODM_RTL8723A)

				ODM_SetBBReg(pDM_Odm, 0x874, BIT5, 0x0); /* Reg874[5]=1b'0 */

				ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x0); /* Reg874[5]=1b'0 */

		}

		pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;

	}
@@ -1491,7 +1491,7 @@ void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) 
		return;



	if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) {		/* at least delay 1 sec */

		PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);

		PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);



		pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;

		return;
@@ -1700,10 +1700,10 @@ u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point, u8 initial_gai 
	ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);



	/* Start PSD calculation, Reg808[22]=0->1 */

	ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1);

	ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 1);

	/* Need to wait for HW PSD report */

	ODM_StallExecution(30);

	ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);

	ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 0);

	/* Read PSD report, Reg8B4[15:0] */

	psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
@@ -1805,11 +1805,11 @@ bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode) 


	if (pDM_Odm->SupportICType == ODM_RTL8192C) {

		/* Which path in ADC/DAC is turnned on for PSD: both I/Q */

		ODM_SetBBReg(pDM_Odm, 0x808, BIT10|BIT11, 0x3);

		ODM_SetBBReg(pDM_Odm, 0x808, BIT(10)|BIT(11), 0x3);

		/* Ageraged number: 8 */

		ODM_SetBBReg(pDM_Odm, 0x808, BIT12|BIT13, 0x1);

		ODM_SetBBReg(pDM_Odm, 0x808, BIT(12)|BIT(13), 0x1);

		/* pts = 128; */

		ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);

		ODM_SetBBReg(pDM_Odm, 0x808, BIT(14)|BIT(15), 0x0);

	}



	/* 1 Backup Current RF/BB Settings */
@@ -1831,7 +1831,7 @@ bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode) 
	odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);



	/* Set PSD 128 pts */

	ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0);  /* 128 pts */

	ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT(14)|BIT(15), 0x0);  /* 128 pts */



	/*  To SET CH1 to do */

	ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01);     /* Channel 1 */

drivers/staging/r8188eu/hal/odm_HWConfig.c

+2 −2
Original line number Diff line number Diff line
@@ -449,7 +449,7 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm, 
				}

			}



			pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0;

			pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT(0);



		} else {

			RSSI_Ave = pPhyInfo->RxPWDBAll;
@@ -478,7 +478,7 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm, 
			pEntry->rssi_stat.ValidBit++;



		for (i = 0; i < pEntry->rssi_stat.ValidBit; i++)

			OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0;

			OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT(0);



		if (pEntry->rssi_stat.ValidBit == 64) {

			Weighting = ((OFDM_pkt<<4) > 64) ? 64 : (OFDM_pkt<<4);

drivers/staging/r8188eu/hal/odm_RTL8188E.c

+58 −58

File changed.

Preview size limit exceeded, changes collapsed.