Commit dc900431 authored by Johan Hovold's avatar Johan Hovold Committed by Shawn Guo
Browse files

arm64: dts: imx8mm-venice: fix spi2 pin configuration 



Due to what looks like a copy-paste error, the ECSPI2_MISO pad is not
muxed for SPI mode and causes reads from a slave-device connected to the
SPI header to always return zero.

Configure the ECSPI2_MISO pad for SPI mode on the gw71xx, gw72xx and
gw73xx families of boards that got this wrong.

Fixes: 6f30b27c ("arm64: dts: imx8mm: Add Gateworks i.MX 8M Mini Development Kits")
Cc: stable@vger.kernel.org      # 5.12
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: default avatarJohan Hovold <johan@kernel.org>
Acked-by: default avatarTim Harvey <tharvey@gateworks.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 9b6d368b

arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -215,7 +215,7 @@ 
		fsl,pins = <

			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6

			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6

			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6

			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6

			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6

		>;

	};

arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -309,7 +309,7 @@ 
		fsl,pins = <

			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6

			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6

			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6

			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6

			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6

		>;

	};

arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -358,7 +358,7 @@ 
		fsl,pins = <

			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6

			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6

			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6

			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6

			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6

		>;

	};