Unverified Commit dc68fe80 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!5543 v2 locking/qspinlock: Add CNA support for ARM64 

Merge Pull Request from: @ci-robot 
 
PR sync from: Wei Li <liwei391@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/PYX3BUC3OGQ6EFNXJYQKH5WR75GJHSBM/ 
Backport CNA support for ARM64 from openEuler-1.0-LTS, with a little
cleanup. 

Wei Li (2):
  locking/qspinlock: Add CNA support for ARM64 without pvspinlock
  config/arm64: Enable numa aware qspinlock by default


-- 
2.25.1
 
https://gitee.com/openeuler/kernel/issues/I8T8XV 
 
Link:https://gitee.com/openeuler/kernel/pulls/5543

 

Reviewed-by: default avatarZhang Jianhua <chris.zjh@huawei.com>
Reviewed-by: default avatarLiu Chao <liuchao173@huawei.com>
Reviewed-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents fe0d22a2 c7fb8b90

arch/arm64/Kconfig

+15 −0
Original line number Diff line number Diff line
@@ -1556,6 +1556,21 @@ config NODES_SHIFT 
	  Specify the maximum number of NUMA Nodes available on the target

	  system.  Increases memory reserved to accommodate various tables.



config NUMA_AWARE_SPINLOCKS

	bool "Numa-aware spinlocks"

	depends on NUMA

	depends on QUEUED_SPINLOCKS

	default n

	help

	  Introduce NUMA (Non Uniform Memory Access) awareness into

	  the slow path of spinlocks.



	  In this variant of qspinlock, the kernel will try to keep the lock

	  on the same node, thus reducing the number of remote cache misses,

	  while trading some of the short term fairness for better performance.



	  Say N if you want absolute first come first serve fairness.



source "kernel/Kconfig.hz"



config ARCH_SPARSEMEM_ENABLE

arch/arm64/configs/openeuler_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -462,6 +462,7 @@ CONFIG_HOTPLUG_CPU=y 
# CONFIG_ARM64_BOOTPARAM_HOTPLUG_CPU0 is not set

CONFIG_NUMA=y

CONFIG_NODES_SHIFT=8

CONFIG_NUMA_AWARE_SPINLOCKS=y

# CONFIG_HZ_100 is not set

CONFIG_HZ_250=y

# CONFIG_HZ_300 is not set

arch/arm64/include/asm/Kbuild

+0 −1
Original line number Diff line number Diff line
@@ -2,7 +2,6 @@ 
generic-y += early_ioremap.h

generic-y += mcs_spinlock.h

generic-y += qrwlock.h

generic-y += qspinlock.h

generic-y += parport.h

generic-y += user.h

arch/arm64/include/asm/qspinlock.h

0 → 100644
+38 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_ARM64_QSPINLOCK_H

#define _ASM_ARM64_QSPINLOCK_H



#ifdef CONFIG_NUMA_AWARE_SPINLOCKS

#include <asm-generic/qspinlock_types.h>



extern void cna_configure_spin_lock_slowpath(void);



extern void (*cna_queued_spin_lock_slowpath)(struct qspinlock *lock, u32 val);

extern void native_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);



#define	queued_spin_unlock queued_spin_unlock

/**

 * queued_spin_unlock - release a queued spinlock

 * @lock : Pointer to queued spinlock structure

 *

 * A smp_store_release() on the least-significant byte.

 */

static inline void native_queued_spin_unlock(struct qspinlock *lock)

{

	smp_store_release(&lock->locked, 0);

}



static inline void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val)

{

	cna_queued_spin_lock_slowpath(lock, val);

}



static inline void queued_spin_unlock(struct qspinlock *lock)

{

	native_queued_spin_unlock(lock);

}

#endif



#include <asm-generic/qspinlock.h>



#endif /* _ASM_ARM64_QSPINLOCK_H */

arch/x86/kernel/alternative.c

+0 −4
Original line number Diff line number Diff line
@@ -1612,10 +1612,6 @@ void __init alternative_instructions(void) 
	 */

	paravirt_set_cap();



#if defined(CONFIG_NUMA_AWARE_SPINLOCKS)

	cna_configure_spin_lock_slowpath();

#endif



	/*

	 * First patch paravirt functions, such that we overwrite the indirect

	 * call with the direct call.