Unverified Commit dc6667a4 authored by Guo Ren's avatar Guo Ren Committed by Palmer Dabbelt
Browse files

riscv: Extending cpufeature.c to detect V-extension 



Add V-extension into riscv_isa_ext_keys array and detect it with isa
string parsing.

Signed-off-by: default avatarGuo Ren <ren_guo@c-sky.com>
Signed-off-by: default avatarGuo Ren <guoren@linux.alibaba.com>
Signed-off-by: default avatarGreentime Hu <greentime.hu@sifive.com>
Suggested-by: default avatarVineet Gupta <vineetg@rivosinc.com>
Co-developed-by: default avatarAndy Chiu <andy.chiu@sifive.com>
Signed-off-by: default avatarAndy Chiu <andy.chiu@sifive.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarHeiko Stuebner <heiko.stuebner@vrull.eu>
Tested-by: default avatarHeiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230605110724.21391-3-andy.chiu@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 419d5d38

arch/riscv/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#define RISCV_ISA_EXT_m		('m' - 'a')

#define RISCV_ISA_EXT_s		('s' - 'a')

#define RISCV_ISA_EXT_u		('u' - 'a')

#define RISCV_ISA_EXT_v		('v' - 'a')



/*

 * These macros represent the logical IDs of each multi-letter RISC-V ISA

arch/riscv/include/asm/vector.h

0 → 100644
+26 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 * Copyright (C) 2020 SiFive

 */



#ifndef __ASM_RISCV_VECTOR_H

#define __ASM_RISCV_VECTOR_H



#include <linux/types.h>



#ifdef CONFIG_RISCV_ISA_V



#include <asm/hwcap.h>



static __always_inline bool has_vector(void)

{

	return riscv_has_extension_unlikely(RISCV_ISA_EXT_v);

}



#else /* ! CONFIG_RISCV_ISA_V  */



static __always_inline bool has_vector(void) { return false; }



#endif /* CONFIG_RISCV_ISA_V */



#endif /* ! __ASM_RISCV_VECTOR_H */

arch/riscv/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -21,5 +21,6 @@ 
#define COMPAT_HWCAP_ISA_F	(1 << ('F' - 'A'))

#define COMPAT_HWCAP_ISA_D	(1 << ('D' - 'A'))

#define COMPAT_HWCAP_ISA_C	(1 << ('C' - 'A'))

#define COMPAT_HWCAP_ISA_V	(1 << ('V' - 'A'))



#endif /* _UAPI_ASM_RISCV_HWCAP_H */

arch/riscv/kernel/cpufeature.c

+11 −0
Original line number Diff line number Diff line
@@ -107,6 +107,7 @@ void __init riscv_fill_hwcap(void) 
	isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;

	isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;

	isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;

	isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;



	elf_hwcap = 0;
@@ -267,6 +268,16 @@ void __init riscv_fill_hwcap(void) 
		elf_hwcap &= ~COMPAT_HWCAP_ISA_F;

	}



	if (elf_hwcap & COMPAT_HWCAP_ISA_V) {

		/*

		 * ISA string in device tree might have 'v' flag, but

		 * CONFIG_RISCV_ISA_V is disabled in kernel.

		 * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled.

		 */

		if (!IS_ENABLED(CONFIG_RISCV_ISA_V))

			elf_hwcap &= ~COMPAT_HWCAP_ISA_V;

	}



	memset(print_str, 0, sizeof(print_str));

	for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)

		if (riscv_isa[0] & BIT_MASK(i))