Commit dc5d5f9d authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Felix Fietkau
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mt76: mt7921: enable sw interrupts



Enable sw interrupts in order to wake the device from deep sleep
receiving packets

Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 36873246
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+1 −0
Original line number Diff line number Diff line
@@ -351,6 +351,7 @@ int mt7921_dma_init(struct mt7921_dev *dev)
	/* enable interrupts for TX/RX rings */
	mt7921_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
			  MT_INT_MCU_CMD);
	mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);

	return 0;
}
+1 −0
Original line number Diff line number Diff line
@@ -1276,6 +1276,7 @@ mt7921_dma_reset(struct mt7921_dev *dev)
	mt7921_irq_enable(dev,
			  MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
			  MT_INT_MCU_CMD);
	mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
}

void mt7921_tx_token_put(struct mt7921_dev *dev)
+13 −0
Original line number Diff line number Diff line
@@ -61,6 +61,18 @@ static void mt7921_irq_tasklet(unsigned long data)
	if (intr & MT_INT_TX_DONE_MCU)
		mask |= MT_INT_TX_DONE_MCU;

	if (intr & MT_INT_MCU_CMD) {
		u32 intr_sw;

		intr_sw = mt76_rr(dev, MT_MCU_CMD);
		/* ack MCU2HOST_SW_INT_STA */
		mt76_wr(dev, MT_MCU_CMD, intr_sw);
		if (intr_sw & MT_MCU_CMD_WAKE_RX_PCIE) {
			mask |= MT_INT_RX_DONE_DATA;
			intr |= MT_INT_RX_DONE_DATA;
		}
	}

	mt76_set_irq_mask(&dev->mt76, MT_WFDMA0_HOST_INT_ENA, mask, 0);

	if (intr & MT_INT_TX_DONE_ALL)
@@ -253,6 +265,7 @@ static int mt7921_pci_resume(struct pci_dev *pdev)
	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
	mt7921_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
			  MT_INT_MCU_CMD);
	mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);

	/* put dma enabled */
	mt76_set(dev, MT_WFDMA0_GLO_CFG,
+10 −7
Original line number Diff line number Diff line
@@ -252,6 +252,7 @@
#define MT_WFDMA0_BUSY_ENA_RX_FIFO	BIT(2)

#define MT_MCU_CMD			MT_WFDMA0(0x1f0)
#define MT_MCU_CMD_WAKE_RX_PCIE		BIT(0)
#define MT_MCU_CMD_STOP_DMA_FW_RELOAD	BIT(1)
#define MT_MCU_CMD_STOP_DMA		BIT(2)
#define MT_MCU_CMD_RESET_DONE		BIT(3)
@@ -259,6 +260,8 @@
#define MT_MCU_CMD_NORMAL_STATE		BIT(5)
#define MT_MCU_CMD_ERROR_MASK		GENMASK(5, 1)

#define MT_MCU2HOST_SW_INT_ENA		MT_WFDMA0(0x1f4)

#define MT_WFDMA0_HOST_INT_STA		MT_WFDMA0(0x200)
#define HOST_RX_DONE_INT_STS0		BIT(0)	/* Rx mcu */
#define HOST_RX_DONE_INT_STS2		BIT(2)	/* Rx data */