Commit dc5d4aff authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amdgpu: Use correct VIEWPORT_DIMENSION for DCN2 



For some reason this file isn't using the appropriate register
headers for DCN headers, which means that on DCN2 we're getting
the VIEWPORT_DIMENSION offset wrong.

This means that we're not correctly carving out the framebuffer
memory correctly for a framebuffer allocated by EFI and
therefore see corruption when loading amdgpu before the display
driver takes over control of the framebuffer scanout.

Fix this by checking the DCE_HWIP and picking the correct offset
accordingly.

Long-term we should expose this info from DC as GMC shouldn't
need to know about DCN registers.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 15084a8e

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+13 −1
Original line number Diff line number Diff line
@@ -72,6 +72,9 @@ 
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0                                                                  0x049d

#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX                                                         2



#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2                                                          0x05ea

#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX                                                 2





static const char *gfxhub_client_ids[] = {

	"CB",
@@ -1134,6 +1137,8 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 
	u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);

	unsigned size;



	/* TODO move to DC so GMC doesn't need to hard-code DCN registers */



	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {

		size = AMDGPU_VBIOS_VGA_ALLOCATION;

	} else {
@@ -1142,7 +1147,6 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 
		switch (adev->ip_versions[DCE_HWIP][0]) {

		case IP_VERSION(1, 0, 0):

		case IP_VERSION(1, 0, 1):

		case IP_VERSION(2, 1, 0):

			viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);

			size = (REG_GET_FIELD(viewport,

					      HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
@@ -1150,6 +1154,14 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 
					      HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *

				4);

			break;

		case IP_VERSION(2, 1, 0):

			viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);

			size = (REG_GET_FIELD(viewport,

					      HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *

				REG_GET_FIELD(viewport,

					      HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *

				4);

			break;

		default:

			viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);

			size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *