Loading arch/x86/include/asm/kvm_host.h +18 −12 Original line number Diff line number Diff line Loading @@ -291,19 +291,25 @@ struct kvm_kernel_irq_routing_entry; * the number of unique SPs that can theoretically be created is 2^n, where n * is the number of bits that are used to compute the role. * * But, even though there are 18 bits in the mask below, not all combinations * of modes and flags are possible. The maximum number of possible upper-level * shadow pages for a single gfn is in the neighborhood of 2^13. * But, even though there are 19 bits in the mask below, not all combinations * of modes and flags are possible: * * - invalid shadow pages are not accounted. * - level is effectively limited to four combinations, not 16 as the number * bits would imply, as 4k SPs are not tracked (allowed to go unsync). * - level is effectively unused for non-PAE paging because there is exactly * one upper level (see 4k SP exception above). * - quadrant is used only for non-PAE paging and is exclusive with * gpte_is_8_bytes. * - execonly and ad_disabled are used only for nested EPT, which makes it * exclusive with quadrant. * - invalid shadow pages are not accounted, so the bits are effectively 18 * * - quadrant will only be used if gpte_is_8_bytes=0 (non-PAE paging); * execonly and ad_disabled are only used for nested EPT which has * gpte_is_8_bytes=1. Therefore, 2 bits are always unused. * * - the 4 bits of level are effectively limited to the values 2/3/4/5, * as 4k SPs are not tracked (allowed to go unsync). In addition non-PAE * paging has exactly one upper level, making level completely redundant * when gpte_is_8_bytes=0. * * - on top of this, smep_andnot_wp and smap_andnot_wp are only set if * cr0_wp=0, therefore these three bits only give rise to 5 possibilities. * * Therefore, the maximum number of possible upper-level shadow pages for a * single gfn is a bit less than 2^13. */ union kvm_mmu_page_role { u32 word; Loading Loading
arch/x86/include/asm/kvm_host.h +18 −12 Original line number Diff line number Diff line Loading @@ -291,19 +291,25 @@ struct kvm_kernel_irq_routing_entry; * the number of unique SPs that can theoretically be created is 2^n, where n * is the number of bits that are used to compute the role. * * But, even though there are 18 bits in the mask below, not all combinations * of modes and flags are possible. The maximum number of possible upper-level * shadow pages for a single gfn is in the neighborhood of 2^13. * But, even though there are 19 bits in the mask below, not all combinations * of modes and flags are possible: * * - invalid shadow pages are not accounted. * - level is effectively limited to four combinations, not 16 as the number * bits would imply, as 4k SPs are not tracked (allowed to go unsync). * - level is effectively unused for non-PAE paging because there is exactly * one upper level (see 4k SP exception above). * - quadrant is used only for non-PAE paging and is exclusive with * gpte_is_8_bytes. * - execonly and ad_disabled are used only for nested EPT, which makes it * exclusive with quadrant. * - invalid shadow pages are not accounted, so the bits are effectively 18 * * - quadrant will only be used if gpte_is_8_bytes=0 (non-PAE paging); * execonly and ad_disabled are only used for nested EPT which has * gpte_is_8_bytes=1. Therefore, 2 bits are always unused. * * - the 4 bits of level are effectively limited to the values 2/3/4/5, * as 4k SPs are not tracked (allowed to go unsync). In addition non-PAE * paging has exactly one upper level, making level completely redundant * when gpte_is_8_bytes=0. * * - on top of this, smep_andnot_wp and smap_andnot_wp are only set if * cr0_wp=0, therefore these three bits only give rise to 5 possibilities. * * Therefore, the maximum number of possible upper-level shadow pages for a * single gfn is a bit less than 2^13. */ union kvm_mmu_page_role { u32 word; Loading