Commit dbec0afc authored by Marc Zyngier's avatar Marc Zyngier Committed by Wentao Guan
Browse files

arm64: Filter out SVE hwcaps when FEAT_SVE isn't implemented 

stable inclusion
from stable-v6.6.79
commit cad0406ad780cfae3c00c01a818afc96f22207f2
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IBXANC

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=cad0406ad780cfae3c00c01a818afc96f22207f2



--------------------------------

commit 064737920bdbca86df91b96aed256e88018fef3a upstream.

The hwcaps code that exposes SVE features to userspace only
considers ID_AA64ZFR0_EL1, while this is only valid when
ID_AA64PFR0_EL1.SVE advertises that SVE is actually supported.

The expectations are that when ID_AA64PFR0_EL1.SVE is 0, the
ID_AA64ZFR0_EL1 register is also 0. So far, so good.

Things become a bit more interesting if the HW implements SME.
In this case, a few ID_AA64ZFR0_EL1 fields indicate *SME*
features. And these fields overlap with their SVE interpretations.
But the architecture says that the SME and SVE feature sets must
match, so we're still hunky-dory.

This goes wrong if the HW implements SME, but not SVE. In this
case, we end-up advertising some SVE features to userspace, even
if the HW has none. That's because we never consider whether SVE
is actually implemented. Oh well.

Fix it by restricting all SVE capabilities to ID_AA64PFR0_EL1.SVE
being non-zero. The HWCAPS documentation is amended to reflect the
actually checks performed by the kernel.

Fixes: 06a916fe ("arm64: Expose SVE2 features for userspace")
Reported-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: stable@vger.kernel.org
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20250107-arm64-2024-dpisa-v5-1-7578da51fc3d@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit cad0406ad780cfae3c00c01a818afc96f22207f2)
Signed-off-by: default avatarWentao Guan <guanwentao@uniontech.com>
parent 7d30c933

Documentation/arch/arm64/elf_hwcaps.rst

+24 −12
Original line number Diff line number Diff line
@@ -174,22 +174,28 @@ HWCAP2_DCPODP 
    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.



HWCAP2_SVE2

    Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.SVEver == 0b0001.



HWCAP2_SVEAES

    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.AES == 0b0001.



HWCAP2_SVEPMULL

    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.AES == 0b0010.



HWCAP2_SVEBITPERM

    Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.BitPerm == 0b0001.



HWCAP2_SVESHA3

    Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.SHA3 == 0b0001.



HWCAP2_SVESM4

    Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.SM4 == 0b0001.



HWCAP2_FLAGM2

    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
@@ -198,16 +204,20 @@ HWCAP2_FRINT 
    Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.



HWCAP2_SVEI8MM

    Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.I8MM == 0b0001.



HWCAP2_SVEF32MM

    Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.F32MM == 0b0001.



HWCAP2_SVEF64MM

    Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.F64MM == 0b0001.



HWCAP2_SVEBF16

    Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.BF16 == 0b0001.



HWCAP2_I8MM

    Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.
@@ -273,7 +283,8 @@ HWCAP2_EBF16 
    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.



HWCAP2_SVE_EBF16

    Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0010.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.BF16 == 0b0010.



HWCAP2_CSSC

    Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0001.
@@ -282,7 +293,8 @@ HWCAP2_RPRFM 
    Functionality implied by ID_AA64ISAR2_EL1.RPRFM == 0b0001.



HWCAP2_SVE2P1

    Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010.

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and

    ID_AA64ZFR0_EL1.SVEver == 0b0010.



HWCAP2_SME2

    Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0001.

arch/arm64/kernel/cpufeature.c

+26 −12
Original line number Diff line number Diff line
@@ -3004,6 +3004,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.matches = match,						\

	}



#define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap)		\

	{									\

		__HWCAP_CAP(#cap, cap_type, cap)				\

		HWCAP_CPUID_MATCH(reg, field, min_value) 			\

		.matches = match,						\

	}



#ifdef CONFIG_ARM64_PTR_AUTH

static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {

	{
@@ -3032,6 +3039,13 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 
};

#endif



#ifdef CONFIG_ARM64_SVE

static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope)

{

	return system_supports_sve() && has_user_cpuid_feature(cap, scope);

}

#endif



static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {

	HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL),

	HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES),
@@ -3069,18 +3083,18 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),

#ifdef CONFIG_ARM64_SVE

	HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),

	HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),

	HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),

	HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),

	HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),

	HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),

	HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),

	HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),

	HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),

	HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),

	HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),

	HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),

	HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),

	HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),

	HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),

	HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),

	HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),

	HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),

	HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),

	HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),

	HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),

	HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),

	HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),

	HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),

	HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),

#endif

	HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS),

#ifdef CONFIG_ARM64_BTI