Commit dbd08c19 authored by Zihao Sheng's avatar Zihao Sheng Committed by mufengyan
Browse files

Support configuration of fastpath feature 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I99GLS


CVE: NA

--------------------------------------------------------

Currently, there is a limitation that fastpath can only
be used in single function on the chip. In order to obtain
the maximum delay benefit under the chip limitation, this
patch adds fastpath configuration in different scenarios,
mainly including the following:
1. Fastpath is turned on when the driver is loaded
and turned off when the driver is unloaded.
2. Fastpath is turned off when SRIOV is enabled and
turned on when SRIOV is disabled. At the same time,
before configuring fastpath in this scenario, it is
necessary to stop the flow to avoid abnormal
problems in the chip.

Signed-off-by: default avatarZihao Sheng <shengzihao1@huawei.com>
parent ba3549f4

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+1 −0
Original line number Diff line number Diff line
@@ -867,6 +867,7 @@ struct hnae3_ae_ops { 
		       enum hnae3_unic_addr_type addr_type);

	int (*get_func_guid)(struct hnae3_handle *handle, u8 *guid);

	void (*set_func_guid)(struct hnae3_handle *handle, u8 *guid);

	int (*set_fastpath)(struct hnae3_ae_dev *ae_dev, bool fastpath_en);

};



struct hnae3_dcb_ops {

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

+1 −0
Original line number Diff line number Diff line
@@ -317,6 +317,7 @@ enum hclge_opcode_type { 


	/* UB commands */

	HCLGE_OPC_COMM_GET_FUNC_GUID	= 0xA001,

	HCLGE_OPC_COMM_CFG_FASTPATH	= 0xA003,

	HCLGE_OPC_ADD_IP_TBL		= 0xA100,

	HCLGE_OPC_DEL_IP_TBL		= 0xA101,

	HCLGE_OPC_COMM_CFG_FUNC_GUID	= 0xA122,

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+36 −4
Original line number Diff line number Diff line
@@ -3454,6 +3454,23 @@ static void hns3_remove(struct pci_dev *pdev) 
	pci_set_drvdata(pdev, NULL);

}



#if IS_ENABLED(CONFIG_UB_UDMA_HNS3)

static int hns3_fastpath_configure(struct pci_dev *pdev, bool fastpath_en)

{

	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);

	int ret;



	if (!hnae3_dev_udma_supported(ae_dev) || !ae_dev->ops->set_fastpath)

		return 0;



	rtnl_lock();

	ret = ae_dev->ops->set_fastpath(ae_dev, fastpath_en);

	rtnl_unlock();



	return ret;

}

#endif



/**

 * hns3_pci_sriov_configure

 * @pdev: pointer to a pci_dev structure
@@ -3464,6 +3481,7 @@ static void hns3_remove(struct pci_dev *pdev) 
 **/

static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)

{

	int num_vfs_pre;

	int ret;



	if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
@@ -3473,12 +3491,26 @@ static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 


	if (num_vfs) {

		ret = pci_enable_sriov(pdev, num_vfs);

		if (ret)

		if (ret) {

			dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);

		else

			return 0;

		}



#if IS_ENABLED(CONFIG_UB_UDMA_HNS3)

		ret = hns3_fastpath_configure(pdev, false);

		if (ret) {

			pci_disable_sriov(pdev);

			return 0;

		}

#endif



		return num_vfs;

	} else if (!pci_vfs_assigned(pdev)) {

		int num_vfs_pre = pci_num_vf(pdev);

#if IS_ENABLED(CONFIG_UB_UDMA_HNS3)

		(void)hns3_fastpath_configure(pdev, true);

#endif



		num_vfs_pre = pci_num_vf(pdev);



		pci_disable_sriov(pdev);

		hns3_clean_vf_config(pdev, num_vfs_pre);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+9 −0
Original line number Diff line number Diff line
@@ -933,6 +933,15 @@ struct hclge_query_wol_supported_cmd { 
	u8 rsv[20];

};



struct hclge_config_fastpath_cmd {

	u8 fastpath_en;

	u8 rsv0[3];

	__le32 ssu_cfg_status;

	__le32 igu_cfg_status;

	__le32 ppp_cfg_status;

	u8 rsv1[8];

};



struct hclge_hw;

int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);

enum hclge_comm_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+74 −0
Original line number Diff line number Diff line
@@ -12422,6 +12422,56 @@ static int hclge_set_wol(struct hnae3_handle *handle, 
	return ret;

}



#if IS_ENABLED(CONFIG_UB_UDMA_HNS3)

static int hclge_set_fastpath_cmd(struct hnae3_ae_dev *ae_dev, bool fastpath_en)

{

	struct hclge_dev *hdev = ae_dev->priv;

	struct hclge_config_fastpath_cmd *req;

	struct hclge_desc desc;



	if (!hnae3_dev_udma_supported(ae_dev))

		return 0;



	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMM_CFG_FASTPATH, false);

	req = (struct hclge_config_fastpath_cmd *)desc.data;

	req->fastpath_en = fastpath_en;



	return hclge_cmd_send(&hdev->hw, &desc, 1);

}



static int hclge_set_fastpath(struct hnae3_ae_dev *ae_dev, bool fastpath_en)

{

	struct hclge_dev *hdev = ae_dev->priv;

	int last_bad_ret = 0;

	int ret;



	ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);

	if (ret)

		return ret;



	ret = hclge_tm_flush_cfg(hdev, true);

	if (ret)

		return ret;



	ret = hclge_set_fastpath_cmd(ae_dev, fastpath_en);

	if (ret) {

		dev_err(&hdev->pdev->dev,

			"failed to set fastpath, ret = %d\n", ret);

		last_bad_ret = ret;

	}



	ret = hclge_tm_flush_cfg(hdev, false);

	if (ret)

		last_bad_ret = ret;



	ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);

	if (ret)

		last_bad_ret = ret;



	return last_bad_ret;

}

#endif



static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)

{

	struct pci_dev *pdev = ae_dev->pdev;
@@ -12605,6 +12655,14 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 
	if (ret)

		goto err_sysfs_unregister;



#if IS_ENABLED(CONFIG_UB_UDMA_HNS3)

	ret = hclge_set_fastpath_cmd(ae_dev, true);

	if (ret) {

		dev_err(&pdev->dev, "failed to init fastpath, ret = %d\n", ret);

		goto err_sysfs_unregister;

	}

#endif



	INIT_KFIFO(hdev->mac_tnl_log);



	hclge_dcb_ops_set(hdev);
@@ -13036,6 +13094,15 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 
		dev_warn(&pdev->dev,

			 "failed to update wol config, ret = %d\n", ret);



#if IS_ENABLED(CONFIG_UB_UDMA_HNS3)

	ret = hclge_set_fastpath_cmd(ae_dev, pci_num_vf(pdev) ? false : true);

	if (ret) {

		dev_err(&pdev->dev, "failed to reset fastpath, ret = %d\n",

			ret);

		return ret;

	}

#endif



	dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",

		 HCLGE_DRIVER_NAME);
@@ -13047,6 +13114,10 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 
	struct hclge_dev *hdev = ae_dev->priv;

	struct hclge_mac *mac = &hdev->hw.mac;



#if IS_ENABLED(CONFIG_UB_UDMA_HNS3)

	(void)hclge_set_fastpath_cmd(ae_dev, false);

#endif



	hclge_unregister_sysfs(hdev);

	hclge_reset_vf_rate(hdev);

	hclge_clear_vf_vlan(hdev);
@@ -13642,6 +13713,9 @@ struct hnae3_ae_ops hclge_ops = { 
	.get_func_guid = hclge_unic_get_func_guid,

	.set_func_guid = hclge_unic_set_func_guid,

#endif

#if IS_ENABLED(CONFIG_UB_UDMA_HNS3)

	.set_fastpath = hclge_set_fastpath,

#endif

};



static struct hnae3_ae_algo ae_algo = {