Commit dbc4c70e authored by Borislav Petkov's avatar Borislav Petkov
Browse files

x86/sev: Get rid of excessive use of defines 



Remove all the defines of masks and bit positions for the GHCB MSR
protocol and use comments instead which correspond directly to the spec
so that following those can be a lot easier and straightforward with the
spec opened in parallel to the code.

Aligh vertically while at it.

No functional changes.

Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Signed-off-by: default avatarBrijesh Singh <brijesh.singh@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20211110220731.2396491-6-brijesh.singh@amd.com
parent 18c3933c

arch/x86/include/asm/sev-common.h

+28 −23
Original line number Diff line number Diff line
@@ -18,20 +18,19 @@ 
/* SEV Information Request/Response */

#define GHCB_MSR_SEV_INFO_RESP		0x001

#define GHCB_MSR_SEV_INFO_REQ		0x002

#define GHCB_MSR_VER_MAX_POS		48

#define GHCB_MSR_VER_MAX_MASK		0xffff

#define GHCB_MSR_VER_MIN_POS		32

#define GHCB_MSR_VER_MIN_MASK		0xffff

#define GHCB_MSR_CBIT_POS		24

#define GHCB_MSR_CBIT_MASK		0xff



#define GHCB_MSR_SEV_INFO(_max, _min, _cbit)	\

	((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) |	\

	 (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) |	\

	 (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) |	\

	/* GHCBData[63:48] */			\

	((((_max) & 0xffff) << 48) |		\

	 /* GHCBData[47:32] */			\

	 (((_min) & 0xffff) << 32) |		\

	 /* GHCBData[31:24] */			\

	 (((_cbit) & 0xff)  << 24) |		\

	 GHCB_MSR_SEV_INFO_RESP)



#define GHCB_MSR_INFO(v)		((v) & 0xfffUL)

#define GHCB_MSR_PROTO_MAX(v)		(((v) >> GHCB_MSR_VER_MAX_POS) & GHCB_MSR_VER_MAX_MASK)

#define GHCB_MSR_PROTO_MIN(v)		(((v) >> GHCB_MSR_VER_MIN_POS) & GHCB_MSR_VER_MIN_MASK)

#define GHCB_MSR_PROTO_MAX(v)		(((v) >> 48) & 0xffff)

#define GHCB_MSR_PROTO_MIN(v)		(((v) >> 32) & 0xffff)



/* CPUID Request/Response */

#define GHCB_MSR_CPUID_REQ		0x004
@@ -47,9 +46,12 @@ 
#define GHCB_CPUID_REQ_ECX		2

#define GHCB_CPUID_REQ_EDX		3

#define GHCB_CPUID_REQ(fn, reg)				\

	/* GHCBData[11:0] */				\

	(GHCB_MSR_CPUID_REQ |				\

		(((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \

		(((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS))

	/* GHCBData[31:12] */				\

	(((unsigned long)(reg) & 0x3) << 30) |		\

	/* GHCBData[63:32] */				\

	(((unsigned long)fn) << 32))



/* AP Reset Hold */

#define GHCB_MSR_AP_RESET_HOLD_REQ	0x006
@@ -64,9 +66,12 @@ 
#define GHCB_MSR_TERM_REASON_SET_MASK	0xf

#define GHCB_MSR_TERM_REASON_POS	16

#define GHCB_MSR_TERM_REASON_MASK	0xff



#define GHCB_SEV_TERM_REASON(reason_set, reason_val)	\

	(((((u64)reason_set) &  GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) | \

	((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS))

	/* GHCBData[15:12] */				\

	(((((u64)reason_set) &  0xf) << 12) |		\

	 /* GHCBData[23:16] */				\

	((((u64)reason_val) & 0xff) << 16))



#define GHCB_SEV_ES_GEN_REQ		0

#define GHCB_SEV_ES_PROT_UNSUPPORTED	1