Commit dbc2309c authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: add hubbub_init related 



Required by display init, also update get_dig_mode

Tested-by: default avatarDaniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: default avatarHansen Dsouza <hansen.dsouza@amd.com>
Reviewed-by: default avatarDuncan Ma <duncan.ma@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8af54c61

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h

+11 −1
Original line number Diff line number Diff line
@@ -172,6 +172,10 @@ struct dcn_hubbub_registers { 
	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;

	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D;

	uint32_t SDPIF_REQUEST_RATE_LIMIT;

	uint32_t DCHUBBUB_SDPIF_CFG0;

	uint32_t DCHUBBUB_SDPIF_CFG1;

	uint32_t DCHUBBUB_CLOCK_CNTL;

	uint32_t DCHUBBUB_MEM_PWR_MODE_CTRL;

};



#define HUBBUB_REG_FIELD_LIST_DCN32(type) \
@@ -362,7 +366,13 @@ struct dcn_hubbub_registers { 
		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;\

		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;\

		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;\

		type SDPIF_REQUEST_RATE_LIMIT

		type SDPIF_REQUEST_RATE_LIMIT;\

		type DISPCLK_R_DCHUBBUB_GATE_DIS;\

		type DCFCLK_R_DCHUBBUB_GATE_DIS;\

		type SDPIF_MAX_NUM_OUTSTANDING;\

		type DCHUBBUB_ARB_MAX_REQ_OUTSTAND;\

		type SDPIF_PORT_CONTROL;\

		type DET_MEM_PWR_LS_MODE





struct dcn_hubbub_shift {

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c

+18 −0
Original line number Diff line number Diff line
@@ -1008,6 +1008,24 @@ static bool hubbub31_verify_allow_pstate_change_high(struct hubbub *hubbub) 
	return false;

}



void hubbub31_init(struct hubbub *hubbub)

{

	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);



	/*Enable clock gate*/

	if (hubbub->ctx->dc->debug.disable_clock_gate) {

		/*done in hwseq*/

		/*REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);*/

		REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL,

				DISPCLK_R_DCHUBBUB_GATE_DIS, 0,

				DCFCLK_R_DCHUBBUB_GATE_DIS, 0);

	}



	/*

	only the DCN will determine when to connect the SDP port

	*/

	REG_UPDATE(DCHUBBUB_SDPIF_CFG0,	SDPIF_PORT_CONTROL, 1);

}

static const struct hubbub_funcs hubbub31_funcs = {

	.update_dchub = hubbub2_update_dchub,

	.init_dchub_sys_ctx = hubbub31_init_dchub_sys_ctx,

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h

+9 −1
Original line number Diff line number Diff line
@@ -42,6 +42,10 @@ 
	SR(DCHUBBUB_COMPBUF_CTRL),\

	SR(COMPBUF_RESERVED_SPACE),\

	SR(DCHUBBUB_DEBUG_CTRL_0),\

	SR(DCHUBBUB_CLOCK_CNTL),\

	SR(DCHUBBUB_SDPIF_CFG0),\

	SR(DCHUBBUB_SDPIF_CFG1),\

	SR(DCHUBBUB_MEM_PWR_MODE_CTRL),\

	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\

	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\

	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\
@@ -120,7 +124,11 @@ 
	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \

	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \

	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \

	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh)

	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh),\

	HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DISPCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\

	HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCFCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\

	HUBBUB_SF(DCHUBBUB_SDPIF_CFG0, SDPIF_PORT_CONTROL, mask_sh),\

	HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh)



int hubbub31_init_dchub_sys_ctx(struct hubbub *hubbub,

		struct dcn_hubbub_phys_addr_config *pa_config);

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c

+29 −0
Original line number Diff line number Diff line
@@ -945,6 +945,35 @@ void hubbub32_force_wm_propagate_to_pipes(struct hubbub *hubbub) 
			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);

}



void hubbub32_init(struct hubbub *hubbub)

{

	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);



	/* Enable clock gate*/

	if (hubbub->ctx->dc->debug.disable_clock_gate) {

		/*done in hwseq*/

		/*REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);*/



		REG_UPDATE_2(DCHUBBUB_CLOCK_CNTL,

			DISPCLK_R_DCHUBBUB_GATE_DIS, 0,

			DCFCLK_R_DCHUBBUB_GATE_DIS, 0);

	}

	/*

	ignore the "df_pre_cstate_req" from the SDP port control.

	only the DCN will determine when to connect the SDP port

	*/

	REG_UPDATE(DCHUBBUB_SDPIF_CFG0,

			SDPIF_PORT_CONTROL, 1);

	/*Set SDP's max outstanding request to 512

	must set the register back to 0 (max outstanding = 256) in zero frame buffer mode*/

	REG_UPDATE(DCHUBBUB_SDPIF_CFG1,

			SDPIF_MAX_NUM_OUTSTANDING, 1);

	/*must set the registers back to 256 in zero frame buffer mode*/

	REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND,

			DCHUBBUB_ARB_MAX_REQ_OUTSTAND, 512,

			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 512);

}



static const struct hubbub_funcs hubbub32_funcs = {

	.update_dchub = hubbub2_update_dchub,

	.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h

+15 −2
Original line number Diff line number Diff line
@@ -83,7 +83,12 @@ 
	SR(DCN_VM_FAULT_ADDR_LSB),\

	SR(DCN_VM_FAULT_CNTL),\

	SR(DCN_VM_FAULT_STATUS),\

	SR(SDPIF_REQUEST_RATE_LIMIT)

	SR(SDPIF_REQUEST_RATE_LIMIT),\

	SR(DCHUBBUB_CLOCK_CNTL),\

	SR(DCHUBBUB_SDPIF_CFG0),\

	SR(DCHUBBUB_SDPIF_CFG1),\

	SR(DCHUBBUB_MEM_PWR_MODE_CTRL)





#define HUBBUB_MASK_SH_LIST_DCN32(mask_sh)\

	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
@@ -96,6 +101,7 @@ 
	HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \

	HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \

	HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \

	HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MAX_REQ_OUTSTAND, mask_sh), \

	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \

	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \

	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \
@@ -161,7 +167,14 @@ 
	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \

	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \

	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh),\

	HUBBUB_SF(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, mask_sh)

	HUBBUB_SF(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, mask_sh),\

	HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DISPCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\

	HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCFCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\

	HUBBUB_SF(DCHUBBUB_SDPIF_CFG0, SDPIF_PORT_CONTROL, mask_sh),\

	HUBBUB_SF(DCHUBBUB_SDPIF_CFG1, SDPIF_MAX_NUM_OUTSTANDING, mask_sh),\

	HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh)







bool hubbub32_program_urgent_watermarks(

		struct hubbub *hubbub,