Commit dbb050d2 authored by Harini Katakam's avatar Harini Katakam Committed by Jakub Kicinski
Browse files

phy: mscc: Add support for RGMII delay configuration 



Add support for optional rx/tx-internal-delay-ps from devicetree.
- When rx/tx-internal-delay-ps is/are specified, these take priority
- When either is absent,
1) use 2ns for respective settings if rgmii-id/rxid/txid is/are present
2) use 0.2ns for respective settings if mode is rgmii

Signed-off-by: default avatarHarini Katakam <harini.katakam@amd.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 31605c01

drivers/net/phy/mscc/mscc_main.c

+29 −6
Original line number Diff line number Diff line
@@ -107,6 +107,9 @@ static const struct vsc8531_edge_rate_table edge_table[] = { 
};

#endif



static const int vsc85xx_internal_delay[] = {200, 800, 1100, 1700, 2000, 2300,

					     2600, 3400};



static int vsc85xx_phy_read_page(struct phy_device *phydev)

{

	return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
@@ -525,8 +528,12 @@ static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl, 
{

	u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1;

	u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1;

	int delay_size = ARRAY_SIZE(vsc85xx_internal_delay);

	struct device *dev = &phydev->mdio.dev;

	u16 reg_val = 0;

	u16 mask = 0;

	s32 rx_delay;

	s32 tx_delay;

	int rc = 0;



	/* For traffic to pass, the VSC8502 family needs the RX_CLK disable bit
@@ -541,12 +548,28 @@ static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl, 
	if (phy_interface_is_rgmii(phydev))

		mask |= rgmii_rx_delay_mask | rgmii_tx_delay_mask;



	rx_delay = phy_get_internal_delay(phydev, dev, vsc85xx_internal_delay,

					  delay_size, true);

	if (rx_delay < 0) {

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||

		    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)

		reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos;

			rx_delay = RGMII_CLK_DELAY_2_0_NS;

		else

			rx_delay = RGMII_CLK_DELAY_0_2_NS;

	}



	tx_delay = phy_get_internal_delay(phydev, dev, vsc85xx_internal_delay,

					  delay_size, false);

	if (tx_delay < 0) {

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||

		    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)

		reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos;

			rx_delay = RGMII_CLK_DELAY_2_0_NS;

		else

			rx_delay = RGMII_CLK_DELAY_0_2_NS;

	}



	reg_val |= rx_delay << rgmii_rx_delay_pos;

	reg_val |= tx_delay << rgmii_tx_delay_pos;



	if (mask)

		rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,