Commit dba8eb83 authored by Chun-Jie Chen's avatar Chun-Jie Chen Committed by Matthias Brugger
Browse files

soc: mediatek: pm-domains: Fix the power glitch issue 



Power reset maybe generate unexpected signal. In order to avoid
the glitch issue, we need to enable isolation first to guarantee the
stable signal when power reset is triggered.

Fixes: 59b644b0 ("soc: mediatek: Add MediaTek SCPSYS power domains")
Signed-off-by: default avatarChun-Jie Chen <chun-jie.chen@mediatek.com>
Signed-off-by: default avatarAllen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Reviewed-by: default avatarMiles Chen <miles.chen@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221014102029.1162-1-allen-kh.cheng@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 830b3c68

drivers/soc/mediatek/mtk-pm-domains.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -275,9 +275,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) 
	clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);

	clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);





	/* subsys power off */

	/* subsys power off */

	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);

	regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);

	regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);

	regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);

	regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);

	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);

	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);

	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);

	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);

	regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);