Commit db8b549b authored by Yicong Yang's avatar Yicong Yang Committed by JangShui Yang
Browse files

arm64: setup: name 'tcr2' register 

mainline inclusion
from mainline-v6.13-rc1
commit 926b66e2ebc8c055b9fea3fb3e5f5b67c80e8e7a
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IB4YD4
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=926b66e2ebc8c055b9fea3fb3e5f5b67c80e8e7a



----------------------------------------------------------------------

TCR2_EL1 introduced some additional controls besides TCR_EL1. Currently
only PIE is supported and enabled by writing TCR2_EL1 directly if PIE
detected.

Introduce a named register 'tcr2' just like 'tcr' we've already had.
It'll be initialized to 0 and updated if certain feature detected and
needs to be enabled. Touch the TCR2_EL1 registers at last with the
updated 'tcr2' value if FEAT_TCR2 supported by checking
ID_AA64MMFR3_EL1.TCRX. Then we can extend the support of other features
controlled by TCR2_EL1.

Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarYicong Yang <yangyicong@hisilicon.com>
Link: https://lore.kernel.org/r/20241102104235.62560-3-yangyicong@huawei.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Conflicts:
	arch/arm64/mm/proc.S
[Context conflicts]
Signed-off-by: default avatarJiangShui Yang <yangjiangshui@h-partners.com>
parent 36795baa

arch/arm64/mm/proc.S

+10 −2
Original line number Diff line number Diff line
@@ -420,10 +420,12 @@ SYM_FUNC_START(__cpu_setup) 
	 */

	mair	.req	x17

	tcr	.req	x16

	tcr2	.req	x15

	mov_q	mair, MAIR_EL1_SET

	mov_q	tcr, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \

			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \

			TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS

	mov	tcr2, xzr



	tcr_clear_errata_bits tcr, x9, x5
@@ -464,11 +466,16 @@ SYM_FUNC_START(__cpu_setup) 
	mov_q	x0, PIE_E1

	msr	REG_PIR_EL1, x0



	mov	x0, TCR2_EL1x_PIE

	msr	REG_TCR2_EL1, x0

	orr	tcr2, tcr2, TCR2_EL1x_PIE



.Lskip_indirection:



	mrs_s	x1, SYS_ID_AA64MMFR3_EL1

	ubfx	x1, x1, #ID_AA64MMFR3_EL1_TCRX_SHIFT, #4

	cbz	x1, 1f

	msr	REG_TCR2_EL1, tcr2

1:



	/*

	 * Prepare SCTLR

	 */
@@ -477,4 +484,5 @@ SYM_FUNC_START(__cpu_setup) 


	.unreq	mair

	.unreq	tcr

	.unreq	tcr2

SYM_FUNC_END(__cpu_setup)