Commit db7c4673 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.2-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Palmer Dabbelt:

 - A few DT bindings fixes to more closely align the ISA string
   requirements between the bindings and the ISA manual.

 - A handful of build error/warning fixes.

 - A fix to move init_cpu_topology() later in the boot flow, so it can
   allocate memory.

 - The IRC channel is now in the MAINTAINERS file, so it's easier to
   find.

* tag 'riscv-for-linus-6.2-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: Move call to init_cpu_topology() to later initialization stage
  riscv/kprobe: Fix instruction simulation of JALR
  riscv: fix -Wundef warning for CONFIG_RISCV_BOOT_SPINWAIT
  MAINTAINERS: add an IRC entry for RISC-V
  RISC-V: fix compile error from deduplicated __ALTERNATIVE_CFG_2
  dt-bindings: riscv: fix single letter canonical order
  dt-bindings: riscv: fix underscore requirement for multi-letter extensions
parents e5eb2b22 c1d61058

Documentation/devicetree/bindings/riscv/cpus.yaml

+1 −1
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ properties: 
      insensitive, letters in the riscv,isa string must be all

      lowercase to simplify parsing.

    $ref: "/schemas/types.yaml#/definitions/string"

    pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$

    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$



  # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here

  timebase-frequency: false

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -17960,6 +17960,7 @@ M: Albert Ou <aou@eecs.berkeley.edu> 
L:	linux-riscv@lists.infradead.org

S:	Supported

Q:	https://patchwork.kernel.org/project/linux-riscv/list/

C:	irc://irc.libera.chat/riscv

P:	Documentation/riscv/patch-acceptance.rst

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git

F:	arch/riscv/

arch/riscv/include/asm/alternative-macros.h

+1 −1
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ 


.macro ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1,	\

				new_c_2, vendor_id_2, errata_id_2, enable_2

	ALTERNATIVE_CFG \old_c, \new_c_1, \vendor_id_1, \errata_id_1, \enable_1

	ALTERNATIVE_CFG "\old_c", "\new_c_1", \vendor_id_1, \errata_id_1, \enable_1

	ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2

.endm

arch/riscv/kernel/head.S

+1 −1
Original line number Diff line number Diff line
@@ -326,7 +326,7 @@ clear_bss_done: 
	call soc_early_init

	tail start_kernel



#if CONFIG_RISCV_BOOT_SPINWAIT

#ifdef CONFIG_RISCV_BOOT_SPINWAIT

.Lsecondary_start:

	/* Set trap vector to spin forever to help debug */

	la a3, .Lsecondary_park

arch/riscv/kernel/probes/simulate-insn.c

+2 −2
Original line number Diff line number Diff line
@@ -71,11 +71,11 @@ bool __kprobes simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *reg 
	u32 rd_index = (opcode >> 7) & 0x1f;

	u32 rs1_index = (opcode >> 15) & 0x1f;



	ret = rv_insn_reg_set_val(regs, rd_index, addr + 4);

	ret = rv_insn_reg_get_val(regs, rs1_index, &base_addr);

	if (!ret)

		return ret;



	ret = rv_insn_reg_get_val(regs, rs1_index, &base_addr);

	ret = rv_insn_reg_set_val(regs, rd_index, addr + 4);

	if (!ret)

		return ret;