Commit db5dfbf5 authored by Yixing Liu's avatar Yixing Liu Committed by Jason Gunthorpe
Browse files

RDMA/hns: Remove the num_cqc_timer variable

The bt number of cqc_timer of HIP09 increases compared with that of HIP08.
Therefore, cqc_timer_bt_num and num_cqc_timer do not match. As a result,
the driver may fail to allocate cqc_timer. So the driver needs to uniquely
uses cqc_timer_bt_num to represent the bt number of cqc_timer.

Fixes: 0e40dc2f ("RDMA/hns: Add timer allocation support for hip08")
Link: https://lore.kernel.org/r/20220429093545.58070-1-liangwenpeng@huawei.com


Signed-off-by: default avatarYixing Liu <liuyixing1@huawei.com>
Signed-off-by: default avatarWenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent e8ea058e
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+0 −1
Original line number Diff line number Diff line
@@ -721,7 +721,6 @@ struct hns_roce_caps {
	u32		num_pi_qps;
	u32		reserved_qps;
	int		num_qpc_timer;
	int		num_cqc_timer;
	u32		num_srqs;
	u32		max_wqes;
	u32		max_srq_wrs;
+1 −2
Original line number Diff line number Diff line
@@ -1975,7 +1975,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
	caps->num_mtpts		= HNS_ROCE_V2_MAX_MTPT_NUM;
	caps->num_pds		= HNS_ROCE_V2_MAX_PD_NUM;
	caps->num_qpc_timer	= HNS_ROCE_V2_MAX_QPC_TIMER_NUM;
	caps->num_cqc_timer	= HNS_ROCE_V2_MAX_CQC_TIMER_NUM;
	caps->cqc_timer_bt_num	= HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM;

	caps->max_qp_init_rdma	= HNS_ROCE_V2_MAX_QP_INIT_RDMA;
	caps->max_qp_dest_rdma	= HNS_ROCE_V2_MAX_QP_DEST_RDMA;
@@ -2271,7 +2271,6 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
	caps->max_rq_sg = roundup_pow_of_two(caps->max_rq_sg);
	caps->max_extend_sg	     = le32_to_cpu(resp_a->max_extend_sg);
	caps->num_qpc_timer	     = le16_to_cpu(resp_a->num_qpc_timer);
	caps->num_cqc_timer	     = le16_to_cpu(resp_a->num_cqc_timer);
	caps->max_srq_sges	     = le16_to_cpu(resp_a->max_srq_sges);
	caps->max_srq_sges = roundup_pow_of_two(caps->max_srq_sges);
	caps->num_aeq_vectors	     = resp_a->num_aeq_vectors;
+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@
#define HNS_ROCE_V2_MAX_SRQ_WR			0x8000
#define HNS_ROCE_V2_MAX_SRQ_SGE			64
#define HNS_ROCE_V2_MAX_CQ_NUM			0x100000
#define HNS_ROCE_V2_MAX_CQC_TIMER_NUM		0x100
#define HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM	0x100
#define HNS_ROCE_V2_MAX_SRQ_NUM			0x100000
#define HNS_ROCE_V2_MAX_CQE_NUM			0x400000
#define HNS_ROCE_V2_MAX_RQ_SGE_NUM		64
+1 −1
Original line number Diff line number Diff line
@@ -737,7 +737,7 @@ static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
		ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
					      HEM_TYPE_CQC_TIMER,
					      hr_dev->caps.cqc_timer_entry_sz,
					      hr_dev->caps.num_cqc_timer, 1);
					      hr_dev->caps.cqc_timer_bt_num, 1);
		if (ret) {
			dev_err(dev,
				"Failed to init CQC timer memory, aborting.\n");