arch/riscv/include/asm/semihost.h
0 → 100644
+26
−0
Loading
Per RISC-V semihosting spec [1], implement semihost.h for the existing Arm semihosting earlycon driver to work on RISC-V. Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1] Signed-off-by:Bin Meng <bmeng@tinylab.org> Tested-by:
Sergey Matyukevich <sergey.matyukevich@syntacore.com> Acked-by:
Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20221209150437.795918-3-bmeng@tinylab.org Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>