Commit db385e0b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "Fixes in clk drivers and some clk rate range fixes in the core as
  well:

   - Make sure the struct clk_rate_request is more sane

   - Remove a WARN_ON that was triggering for clks with no parents that
     can change frequency

   - Fix bad i2c bus transactions on Renesas rs9

   - Actually return an error in clk_mt8195_topck_probe() on an error
     path

   - Keep the GPU memories powered while the clk isn't enabled on
     Qualcomm's sc7280 SoC

   - Fix the parent clk for HSCIF modules on Renesas' R-Car V4H SoC"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: qcom: Update the force mem core bit for GPU clocks
  clk: Initialize max_rate in struct clk_rate_request
  clk: Initialize the clk_rate_request even if clk_core is NULL
  clk: Remove WARN_ON NULL parent in clk_core_init_rate_req()
  clk: renesas: r8a779g0: Fix HSCIF parent clocks
  clk: renesas: r8a779g0: Add SASYNCPER clocks
  clk: mediatek: clk-mt8195-topckgen: Fix error return code in clk_mt8195_topck_probe()
  clk: sifive: select by default if SOC_SIFIVE
  clk: rs9: Fix I2C accessors
parents ee6050c8 ffa20aa5

drivers/clk/clk-renesas-pcie.c

+62 −3
Original line number Diff line number Diff line
@@ -90,13 +90,66 @@ static const struct regmap_access_table rs9_writeable_table = { 
	.n_yes_ranges = ARRAY_SIZE(rs9_writeable_ranges),

};



static int rs9_regmap_i2c_write(void *context,

				unsigned int reg, unsigned int val)

{

	struct i2c_client *i2c = context;

	const u8 data[3] = { reg, 1, val };

	const int count = ARRAY_SIZE(data);

	int ret;



	ret = i2c_master_send(i2c, data, count);

	if (ret == count)

		return 0;

	else if (ret < 0)

		return ret;

	else

		return -EIO;

}



static int rs9_regmap_i2c_read(void *context,

			       unsigned int reg, unsigned int *val)

{

	struct i2c_client *i2c = context;

	struct i2c_msg xfer[2];

	u8 txdata = reg;

	u8 rxdata[2];

	int ret;



	xfer[0].addr = i2c->addr;

	xfer[0].flags = 0;

	xfer[0].len = 1;

	xfer[0].buf = (void *)&txdata;



	xfer[1].addr = i2c->addr;

	xfer[1].flags = I2C_M_RD;

	xfer[1].len = 2;

	xfer[1].buf = (void *)rxdata;



	ret = i2c_transfer(i2c->adapter, xfer, 2);

	if (ret < 0)

		return ret;

	if (ret != 2)

		return -EIO;



	/*

	 * Byte 0 is transfer length, which is always 1 due

	 * to BCP register programming to 1 in rs9_probe(),

	 * ignore it and use data from Byte 1.

	 */

	*val = rxdata[1];

	return 0;

}



static const struct regmap_config rs9_regmap_config = {

	.reg_bits = 8,

	.val_bits = 8,

	.cache_type = REGCACHE_FLAT,

	.max_register = 0x8,

	.cache_type = REGCACHE_NONE,

	.max_register = RS9_REG_BCP,

	.rd_table = &rs9_readable_table,

	.wr_table = &rs9_writeable_table,

	.reg_write = rs9_regmap_i2c_write,

	.reg_read = rs9_regmap_i2c_read,

};



static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx)
@@ -242,11 +295,17 @@ static int rs9_probe(struct i2c_client *client) 
			return ret;

	}



	rs9->regmap = devm_regmap_init_i2c(client, &rs9_regmap_config);

	rs9->regmap = devm_regmap_init(&client->dev, NULL,

				       client, &rs9_regmap_config);

	if (IS_ERR(rs9->regmap))

		return dev_err_probe(&client->dev, PTR_ERR(rs9->regmap),

				     "Failed to allocate register map\n");



	/* Always read back 1 Byte via I2C */

	ret = regmap_write(rs9->regmap, RS9_REG_BCP, 1);

	if (ret < 0)

		return ret;



	/* Register clock */

	for (i = 0; i < rs9->chip_info->num_clks; i++) {

		snprintf(name, 5, "DIF%d", i);

drivers/clk/clk.c

+5 −1
Original line number Diff line number Diff line
@@ -1459,10 +1459,14 @@ static void clk_core_init_rate_req(struct clk_core * const core, 
{

	struct clk_core *parent;



	if (WARN_ON(!core || !req))

	if (WARN_ON(!req))

		return;



	memset(req, 0, sizeof(*req));

	req->max_rate = ULONG_MAX;



	if (!core)

		return;



	req->rate = rate;

	clk_core_get_boundaries(core, &req->min_rate, &req->max_rate);

drivers/clk/mediatek/clk-mt8195-topckgen.c

+3 −1
Original line number Diff line number Diff line
@@ -1270,8 +1270,10 @@ static int clk_mt8195_topck_probe(struct platform_device *pdev) 
	hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_parents,

				      ARRAY_SIZE(mfg_fast_parents), CLK_SET_RATE_PARENT,

				      (base + 0x250), 8, 1, 0, &mt8195_clk_lock);

	if (IS_ERR(hw))

	if (IS_ERR(hw)) {

		r = PTR_ERR(hw);

		goto unregister_muxes;

	}

	top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw;



	r = clk_mt8195_reg_mfg_mux_notifier(&pdev->dev,

drivers/clk/qcom/gcc-sc7280.c

+1 −0
Original line number Diff line number Diff line
@@ -3467,6 +3467,7 @@ static int gcc_sc7280_probe(struct platform_device *pdev) 
	regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));

	regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0));

	regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));

	regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13));



	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,

			ARRAY_SIZE(gcc_dfs_clocks));

drivers/clk/qcom/gpucc-sc7280.c

+1 −0
Original line number Diff line number Diff line
@@ -463,6 +463,7 @@ static int gpu_cc_sc7280_probe(struct platform_device *pdev) 
	 */

	regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0));

	regmap_update_bits(regmap, 0x1098, BIT(0), BIT(0));

	regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13));



	return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap);

}