Unverified Commit db10eced authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!1920 net/hinic3: Add DPU PF device type support. 

Merge Pull Request from: @aspiresky01 
 
net/hinic3: Add DPU PF device type support.

https://gitee.com/openeuler/kernel/issues/I7WTFD 
 
Link:https://gitee.com/openeuler/kernel/pulls/1920

 

Reviewed-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 4ffd72b5 2f357c6a

drivers/net/ethernet/huawei/hinic3/hw/hinic3_lld.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -1291,10 +1291,10 @@ EXPORT_SYMBOL(hinic3_set_vf_service_state); 




/*lint -save -e133 -e10*/

/*lint -save -e133 -e10*/

static const struct pci_device_id hinic3_pci_table[] = {

static const struct pci_device_id hinic3_pci_table[] = {

	{PCI_VDEVICE(HUAWEI, HINIC3_DEV_ID_SPU), 0},

	{PCI_VDEVICE(HUAWEI, HINIC3_DEV_ID_STANDARD), 0},

	{PCI_VDEVICE(HUAWEI, HINIC3_DEV_ID_STANDARD), 0},

	{PCI_VDEVICE(HUAWEI, HINIC3_DEV_ID_SDI_5_1_PF), 0},

	{PCI_VDEVICE(HUAWEI, HINIC3_DEV_ID_DPU_PF), 0},

	{PCI_VDEVICE(HUAWEI, HINIC3_DEV_ID_SDI_5_0_PF), 0},

	{PCI_VDEVICE(HUAWEI, HINIC3_DEV_ID_SDI_5_0_PF), 0},

	{PCI_VDEVICE(HUAWEI, HINIC3_DEV_ID_SDI_5_1_PF), 0},

	{PCI_VDEVICE(HUAWEI, HINIC3_DEV_ID_VF), 0},

	{PCI_VDEVICE(HUAWEI, HINIC3_DEV_ID_VF), 0},

	{0, 0}

	{0, 0}

drivers/net/ethernet/huawei/hinic3/hw/hinic3_pci_id_tbl.h

+4 −1
Original line number Original line Diff line number Diff line
@@ -5,11 +5,14 @@ 
#define HINIC3_PCI_ID_TBL_H

#define HINIC3_PCI_ID_TBL_H





#define PCI_VENDOR_ID_HUAWEI			0x19e5

#define PCI_VENDOR_ID_HUAWEI			0x19e5



#define HINIC3_DEV_ID_STANDARD			0x0222

#define HINIC3_DEV_ID_STANDARD			0x0222

#define HINIC3_DEV_ID_SDI_5_1_PF		0x0226

#define HINIC3_DEV_ID_DPU_PF		        0x0224

#define HINIC3_DEV_ID_SDI_5_0_PF		0x0225

#define HINIC3_DEV_ID_SDI_5_0_PF		0x0225

#define HINIC3_DEV_ID_SDI_5_1_PF		0x0226

#define HINIC3_DEV_ID_VF			0x375F

#define HINIC3_DEV_ID_VF			0x375F

#define HINIC3_DEV_ID_VF_HV			0x379F

#define HINIC3_DEV_ID_VF_HV			0x379F

#define HINIC3_DEV_ID_SPU			0xAC00

#define HINIC3_DEV_ID_SPU			0xAC00



#endif

#endif