Commit daf3af47 authored by Thomas Gleixner's avatar Thomas Gleixner
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x86/apic: Clarify i82489DX bit overlap in APIC_LVT0 



Daniel stumbled over the bit overlap of the i82498DX external APIC and the
TSC deadline timer configuration bit in modern APICs, which is neither
documented in the code nor in the current SDM. Maciej provided links to
the original i82489DX/486 documentation. See Link.

Remove the i82489DX macro maze, use a i82489DX specific define in the apic
code and document the overlap in a comment.

Reported-by: default avatarDaniel Vacek <neelx@redhat.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Maciej W. Rozycki <macro@orcam.me.uk>
Link: https://lore.kernel.org/r/87ee22f3ci.ffs@tglx
parent ce522ba9

arch/x86/include/asm/apicdef.h

+0 −6
Original line number Diff line number Diff line
@@ -95,12 +95,6 @@ 
#define	APIC_LVTTHMR	0x330

#define	APIC_LVTPC	0x340

#define	APIC_LVT0	0x350

#define		APIC_LVT_TIMER_BASE_MASK	(0x3 << 18)

#define		GET_APIC_TIMER_BASE(x)		(((x) >> 18) & 0x3)

#define		SET_APIC_TIMER_BASE(x)		(((x) << 18))

#define		APIC_TIMER_BASE_CLKIN		0x0

#define		APIC_TIMER_BASE_TMBASE		0x1

#define		APIC_TIMER_BASE_DIV		0x2

#define		APIC_LVT_TIMER_ONESHOT		(0 << 17)

#define		APIC_LVT_TIMER_PERIODIC		(1 << 17)

#define		APIC_LVT_TIMER_TSCDEADLINE	(2 << 17)

arch/x86/kernel/apic/apic.c

+10 −1
Original line number Diff line number Diff line
@@ -320,6 +320,9 @@ int lapic_get_maxlvt(void) 
#define APIC_DIVISOR 16

#define TSC_DIVISOR  8



/* i82489DX specific */

#define		I82489DX_BASE_DIVIDER		(((0x2) << 18))



/*

 * This function sets up the local APIC timer, with a timeout of

 * 'clocks' APIC bus clock. During calibration we actually call
@@ -340,8 +343,14 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 
	else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))

		lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;



	/*

	 * The i82489DX APIC uses bit 18 and 19 for the base divider.  This

	 * overlaps with bit 18 on integrated APICs, but is not documented

	 * in the SDM. No problem though. i82489DX equipped systems do not

	 * have TSC deadline timer.

	 */

	if (!lapic_is_integrated())

		lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);

		lvtt_value |= I82489DX_BASE_DIVIDER;



	if (!irqen)

		lvtt_value |= APIC_LVT_MASKED;