Commit dacca1e5 authored by Tony W Wang-oc's avatar Tony W Wang-oc Committed by Dave Hansen
Browse files

x86/acpi/cstate: Optimize ARB_DISABLE on Centaur CPUs 



On all recent Centaur platforms, ARB_DISABLE is handled by PMU
automatically while entering C3 type state. No need for OS to
issue the ARB_DISABLE, so set bm_control to zero to indicate that.

Signed-off-by: default avatarTony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Acked-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://lore.kernel.org/all/1667792089-4904-1-git-send-email-TonyWWang-oc%40zhaoxin.com
parent f8bd9f25

arch/x86/kernel/acpi/cstate.c

+16 −8
Original line number Diff line number Diff line
@@ -52,6 +52,10 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, 
	if (c->x86_vendor == X86_VENDOR_INTEL &&

	    (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))

			flags->bm_control = 0;



	if (c->x86_vendor == X86_VENDOR_CENTAUR) {

		if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f &&

		    c->x86_stepping >= 0x0e)) {

			/*

			 * For all recent Centaur CPUs, the ucode will make sure that each

			 * core can keep cache coherence with each other while entering C3
@@ -59,10 +63,14 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, 
			 * doesn't need to execute a cache flush operation (WBINVD) when

			 * entering C3 type state.

			 */

	if (c->x86_vendor == X86_VENDOR_CENTAUR) {

		if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f &&

		    c->x86_stepping >= 0x0e))

			flags->bm_check = 1;

			/*

			 * For all recent Centaur platforms, ARB_DISABLE is a nop.

			 * Set bm_control to zero to indicate that ARB_DISABLE is

			 * not required while entering C3 type state.

			 */

			flags->bm_control = 0;

		}

	}



	if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {