Unverified Commit dab8c5b9 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!4670 crypto HiSilicon round main line code 

Merge Pull Request from: @xiao_jiang_shui 
 
### The main features of this round are as follows:
* 1.zip support deflate algorithm
* 2.zip remove zlib and gzip
* 3.zip add zip comp high perf mode configuration
* 4.qm obtain stop queue status

### In addition, some bugfixes and cleanup are performed. For details, see the patch description.

issue: https://gitee.com/openeuler/kernel/issues/I925L9 
 
Link:https://gitee.com/openeuler/kernel/pulls/4670

 

Reviewed-by: default avatarYang Shen <shenyang39@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents b24b5c65 5c310d4a

Documentation/ABI/testing/debugfs-hisi-hpre

+23 −1
Original line number Diff line number Diff line
@@ -101,7 +101,7 @@ What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/status 
Date:		Apr 2020

Contact:	linux-crypto@vger.kernel.org

Description:	Dump the status of the QM.

		Four states: initiated, started, stopped and closed.

		Two states: work, stop.

		Available for both PF and VF, and take no other effect on HPRE.



What:		/sys/kernel/debug/hisi_hpre/<bdf>/qm/diff_regs
@@ -111,6 +111,28 @@ Description: QM debug registers(regs) read hardware register value. This 
		node is used to show the change of the qm register values. This

		node can be help users to check the change of register values.



What:		/sys/kernel/debug/hisi_hpre/<bdf>/qm/qm_state

Date:		Jan 2024

Contact:	linux-crypto@vger.kernel.org

Description:	Dump the state of the device.

		0: busy, 1: idle.

		Only available for PF, and take no other effect on HPRE.



What:		/sys/kernel/debug/hisi_hpre/<bdf>/qm/dev_timeout

Date:		Feb 2024

Contact:	linux-crypto@vger.kernel.org

Description:	Set the wait time when stop queue fails. Available for both PF

		and VF, and take no other effect on HPRE.

		0: not wait(default), others value: wait dev_timeout * 20 microsecond.



What:		/sys/kernel/debug/hisi_hpre/<bdf>/qm/dev_state

Date:		Feb 2024

Contact:	linux-crypto@vger.kernel.org

Description:	Dump the stop queue status of the QM. The default value is 0,

		if dev_timeout is set, when stop queue fails, the dev_state

		will return non-zero value. Available for both PF and VF,

		and take no other effect on HPRE.



What:		/sys/kernel/debug/hisi_hpre/<bdf>/hpre_dfx/diff_regs

Date:		Mar 2022

Contact:	linux-crypto@vger.kernel.org

Documentation/ABI/testing/debugfs-hisi-sec

+23 −1
Original line number Diff line number Diff line
@@ -81,7 +81,7 @@ What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/status 
Date:		Apr 2020

Contact:	linux-crypto@vger.kernel.org

Description:	Dump the status of the QM.

		Four states: initiated, started, stopped and closed.

		Two states: work, stop.

		Available for both PF and VF, and take no other effect on SEC.



What:		/sys/kernel/debug/hisi_sec2/<bdf>/qm/diff_regs
@@ -91,6 +91,28 @@ Description: QM debug registers(regs) read hardware register value. This 
		node is used to show the change of the qm register values. This

		node can be help users to check the change of register values.



What:		/sys/kernel/debug/hisi_sec2/<bdf>/qm/qm_state

Date:		Jan 2024

Contact:	linux-crypto@vger.kernel.org

Description:	Dump the state of the device.

		0: busy, 1: idle.

		Only available for PF, and take no other effect on SEC.



What:		/sys/kernel/debug/hisi_sec2/<bdf>/qm/dev_timeout

Date:		Feb 2024

Contact:	linux-crypto@vger.kernel.org

Description:	Set the wait time when stop queue fails. Available for both PF

		and VF, and take no other effect on SEC.

		0: not wait(default), others value: wait dev_timeout * 20 microsecond.



What:		/sys/kernel/debug/hisi_sec2/<bdf>/qm/dev_state

Date:		Feb 2024

Contact:	linux-crypto@vger.kernel.org

Description:	Dump the stop queue status of the QM. The default value is 0,

		if dev_timeout is set, when stop queue fails, the dev_state

		will return non-zero value. Available for both PF and VF,

		and take no other effect on SEC.



What:		/sys/kernel/debug/hisi_sec2/<bdf>/sec_dfx/diff_regs

Date:		Mar 2022

Contact:	linux-crypto@vger.kernel.org

Documentation/ABI/testing/debugfs-hisi-zip

+23 −1
Original line number Diff line number Diff line
@@ -94,7 +94,7 @@ What: /sys/kernel/debug/hisi_zip/<bdf>/qm/status 
Date:		Apr 2020

Contact:	linux-crypto@vger.kernel.org

Description:	Dump the status of the QM.

		Four states: initiated, started, stopped and closed.

		Two states: work, stop.

		Available for both PF and VF, and take no other effect on ZIP.



What:		/sys/kernel/debug/hisi_zip/<bdf>/qm/diff_regs
@@ -104,6 +104,28 @@ Description: QM debug registers(regs) read hardware register value. This 
		node is used to show the change of the qm registers value. This

		node can be help users to check the change of register values.



What:		/sys/kernel/debug/hisi_zip/<bdf>/qm/qm_state

Date:		Jan 2024

Contact:	linux-crypto@vger.kernel.org

Description:	Dump the state of the device.

		0: busy, 1: idle.

		Only available for PF, and take no other effect on ZIP.



What:		/sys/kernel/debug/hisi_zip/<bdf>/qm/dev_timeout

Date:		Feb 2024

Contact:	linux-crypto@vger.kernel.org

Description:	Set the wait time when stop queue fails. Available for both PF

		and VF, and take no other effect on ZIP.

		0: not wait(default), others value: wait dev_timeout * 20 microsecond.



What:		/sys/kernel/debug/hisi_zip/<bdf>/qm/dev_state

Date:		Feb 2024

Contact:	linux-crypto@vger.kernel.org

Description:	Dump the stop queue status of the QM. The default value is 0,

		if dev_timeout is set, when stop queue fails, the dev_state

		will return non-zero value. Available for both PF and VF,

		and take no other effect on ZIP.



What:		/sys/kernel/debug/hisi_zip/<bdf>/zip_dfx/diff_regs

Date:		Mar 2022

Contact:	linux-crypto@vger.kernel.org

drivers/crypto/hisilicon/debugfs.c

+117 −70
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@ 
#define QM_DFX_QN_SHIFT			16

#define QM_DFX_CNT_CLR_CE		0x100118

#define QM_DBG_WRITE_LEN		1024

#define QM_IN_IDLE_ST_REG		0x1040e4

#define QM_IN_IDLE_STATE		0x1



static const char * const qm_debug_file_name[] = {

	[CURRENT_QM]   = "current_qm",
@@ -31,6 +33,10 @@ static const char * const qm_debug_file_name[] = { 
	[CLEAR_ENABLE] = "clear_enable",

};



static const char * const qm_s[] = {

	"work", "stop",

};



struct qm_dfx_item {

	const char *name;

	u32 offset;
@@ -53,34 +59,58 @@ static struct qm_dfx_item qm_dfx_files[] = { 
#define CNT_CYC_REGS_NUM		10

static const struct debugfs_reg32 qm_dfx_regs[] = {

	/* XXX_CNT are reading clear register */

	{"QM_ECC_1BIT_CNT               ",  0x104000ull},

	{"QM_ECC_MBIT_CNT               ",  0x104008ull},

	{"QM_DFX_MB_CNT                 ",  0x104018ull},

	{"QM_DFX_DB_CNT                 ",  0x104028ull},

	{"QM_DFX_SQE_CNT                ",  0x104038ull},

	{"QM_DFX_CQE_CNT                ",  0x104048ull},

	{"QM_DFX_SEND_SQE_TO_ACC_CNT    ",  0x104050ull},

	{"QM_DFX_WB_SQE_FROM_ACC_CNT    ",  0x104058ull},

	{"QM_DFX_ACC_FINISH_CNT         ",  0x104060ull},

	{"QM_DFX_CQE_ERR_CNT            ",  0x1040b4ull},

	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200ull},

	{"QM_ECC_1BIT_INF               ",  0x104004ull},

	{"QM_ECC_MBIT_INF               ",  0x10400cull},

	{"QM_DFX_ACC_RDY_VLD0           ",  0x1040a0ull},

	{"QM_DFX_ACC_RDY_VLD1           ",  0x1040a4ull},

	{"QM_DFX_AXI_RDY_VLD            ",  0x1040a8ull},

	{"QM_DFX_FF_ST0                 ",  0x1040c8ull},

	{"QM_DFX_FF_ST1                 ",  0x1040ccull},

	{"QM_DFX_FF_ST2                 ",  0x1040d0ull},

	{"QM_DFX_FF_ST3                 ",  0x1040d4ull},

	{"QM_DFX_FF_ST4                 ",  0x1040d8ull},

	{"QM_DFX_FF_ST5                 ",  0x1040dcull},

	{"QM_DFX_FF_ST6                 ",  0x1040e0ull},

	{"QM_IN_IDLE_ST                 ",  0x1040e4ull},

	{"QM_ECC_1BIT_CNT               ",  0x104000},

	{"QM_ECC_MBIT_CNT               ",  0x104008},

	{"QM_DFX_MB_CNT                 ",  0x104018},

	{"QM_DFX_DB_CNT                 ",  0x104028},

	{"QM_DFX_SQE_CNT                ",  0x104038},

	{"QM_DFX_CQE_CNT                ",  0x104048},

	{"QM_DFX_SEND_SQE_TO_ACC_CNT    ",  0x104050},

	{"QM_DFX_WB_SQE_FROM_ACC_CNT    ",  0x104058},

	{"QM_DFX_ACC_FINISH_CNT         ",  0x104060},

	{"QM_DFX_CQE_ERR_CNT            ",  0x1040b4},

	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200},

	{"QM_ECC_1BIT_INF               ",  0x104004},

	{"QM_ECC_MBIT_INF               ",  0x10400c},

	{"QM_DFX_ACC_RDY_VLD0           ",  0x1040a0},

	{"QM_DFX_ACC_RDY_VLD1           ",  0x1040a4},

	{"QM_DFX_AXI_RDY_VLD            ",  0x1040a8},

	{"QM_DFX_FF_ST0                 ",  0x1040c8},

	{"QM_DFX_FF_ST1                 ",  0x1040cc},

	{"QM_DFX_FF_ST2                 ",  0x1040d0},

	{"QM_DFX_FF_ST3                 ",  0x1040d4},

	{"QM_DFX_FF_ST4                 ",  0x1040d8},

	{"QM_DFX_FF_ST5                 ",  0x1040dc},

	{"QM_DFX_FF_ST6                 ",  0x1040e0},

	{"QM_IN_IDLE_ST                 ",  0x1040e4},

	{"QM_CACHE_CTL                  ",  0x100050},

	{"QM_TIMEOUT_CFG                ",  0x100070},

	{"QM_DB_TIMEOUT_CFG             ",  0x100074},

	{"QM_FLR_PENDING_TIME_CFG       ",  0x100078},

	{"QM_ARUSR_MCFG1                ",  0x100088},

	{"QM_AWUSR_MCFG1                ",  0x100098},

	{"QM_AXI_M_CFG_ENABLE           ",  0x1000B0},

	{"QM_RAS_CE_THRESHOLD           ",  0x1000F8},

	{"QM_AXI_TIMEOUT_CTRL           ",  0x100120},

	{"QM_AXI_TIMEOUT_STATUS         ",  0x100124},

	{"QM_CQE_AGGR_TIMEOUT_CTRL      ",  0x100144},

	{"ACC_RAS_MSI_INT_SEL           ",  0x1040fc},

	{"QM_CQE_OUT                    ",  0x104100},

	{"QM_EQE_OUT                    ",  0x104104},

	{"QM_AEQE_OUT                   ",  0x104108},

	{"QM_DB_INFO0                   ",  0x104180},

	{"QM_DB_INFO1                   ",  0x104184},

	{"QM_AM_CTRL_GLOBAL             ",  0x300000},

	{"QM_AM_CURR_PORT_STS           ",  0x300100},

	{"QM_AM_CURR_TRANS_RETURN       ",  0x300150},

	{"QM_AM_CURR_RD_MAX_TXID        ",  0x300154},

	{"QM_AM_CURR_WR_MAX_TXID        ",  0x300158},

	{"QM_AM_ALARM_RRESP             ",  0x300180},

	{"QM_AM_ALARM_BRESP             ",  0x300184},

};



static const struct debugfs_reg32 qm_vf_dfx_regs[] = {

	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200ull},

	{"QM_DFX_FUNS_ACTIVE_ST         ",  0x200},

};



/* define the QM's dfx regs region and region length */
@@ -137,8 +167,8 @@ static void dump_show(struct hisi_qm *qm, void *info, 
static int qm_sqc_dump(struct hisi_qm *qm, char *s, char *name)

{

	struct device *dev = &qm->pdev->dev;

	struct qm_sqc *sqc, *sqc_curr;

	dma_addr_t sqc_dma;

	struct qm_sqc *sqc_curr;

	struct qm_sqc sqc;

	u32 qp_id;

	int ret;
@@ -151,35 +181,29 @@ static int qm_sqc_dump(struct hisi_qm *qm, char *s, char *name) 
		return -EINVAL;

	}



	sqc = hisi_qm_ctx_alloc(qm, sizeof(*sqc), &sqc_dma);

	if (IS_ERR(sqc))

		return PTR_ERR(sqc);

	ret = qm_set_and_get_xqc(qm, QM_MB_CMD_SQC, &sqc, qp_id, 1);

	if (!ret) {

		dump_show(qm, &sqc, sizeof(struct qm_sqc), name);



		return 0;

	}



	ret = hisi_qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 1);

	if (ret) {

	down_read(&qm->qps_lock);

	if (qm->sqc) {

		sqc_curr = qm->sqc + qp_id;



			dump_show(qm, sqc_curr, sizeof(*sqc), "SOFT SQC");

		dump_show(qm, sqc_curr, sizeof(*sqc_curr), "SOFT SQC");

	}

	up_read(&qm->qps_lock);



		goto free_ctx;

	}



	dump_show(qm, sqc, sizeof(*sqc), name);



free_ctx:

	hisi_qm_ctx_free(qm, sizeof(*sqc), sqc, &sqc_dma);

	return 0;

}



static int qm_cqc_dump(struct hisi_qm *qm, char *s, char *name)

{

	struct device *dev = &qm->pdev->dev;

	struct qm_cqc *cqc, *cqc_curr;

	dma_addr_t cqc_dma;

	struct qm_cqc *cqc_curr;

	struct qm_cqc cqc;

	u32 qp_id;

	int ret;
@@ -192,34 +216,29 @@ static int qm_cqc_dump(struct hisi_qm *qm, char *s, char *name) 
		return -EINVAL;

	}



	cqc = hisi_qm_ctx_alloc(qm, sizeof(*cqc), &cqc_dma);

	if (IS_ERR(cqc))

		return PTR_ERR(cqc);

	ret = qm_set_and_get_xqc(qm, QM_MB_CMD_CQC, &cqc, qp_id, 1);

	if (!ret) {

		dump_show(qm, &cqc, sizeof(struct qm_cqc), name);



		return 0;

	}



	ret = hisi_qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 1);

	if (ret) {

	down_read(&qm->qps_lock);

	if (qm->cqc) {

		cqc_curr = qm->cqc + qp_id;



			dump_show(qm, cqc_curr, sizeof(*cqc), "SOFT CQC");

		dump_show(qm, cqc_curr, sizeof(*cqc_curr), "SOFT CQC");

	}

	up_read(&qm->qps_lock);



		goto free_ctx;

	}



	dump_show(qm, cqc, sizeof(*cqc), name);



free_ctx:

	hisi_qm_ctx_free(qm, sizeof(*cqc), cqc, &cqc_dma);

	return 0;

}



static int qm_eqc_aeqc_dump(struct hisi_qm *qm, char *s, char *name)

{

	struct device *dev = &qm->pdev->dev;

	dma_addr_t xeqc_dma;

	struct qm_aeqc aeqc;

	struct qm_eqc eqc;

	size_t size;

	void *xeqc;

	int ret;
@@ -233,23 +252,19 @@ static int qm_eqc_aeqc_dump(struct hisi_qm *qm, char *s, char *name) 
	if (!strcmp(name, "EQC")) {

		cmd = QM_MB_CMD_EQC;

		size = sizeof(struct qm_eqc);

		xeqc = &eqc;

	} else {

		cmd = QM_MB_CMD_AEQC;

		size = sizeof(struct qm_aeqc);

		xeqc = &aeqc;

	}



	xeqc = hisi_qm_ctx_alloc(qm, size, &xeqc_dma);

	if (IS_ERR(xeqc))

		return PTR_ERR(xeqc);



	ret = hisi_qm_mb(qm, cmd, xeqc_dma, 0, 1);

	ret = qm_set_and_get_xqc(qm, cmd, xeqc, 0, 1);

	if (ret)

		goto err_free_ctx;

		return ret;



	dump_show(qm, xeqc, size, name);



err_free_ctx:

	hisi_qm_ctx_free(qm, size, xeqc, &xeqc_dma);

	return ret;

}
@@ -1012,6 +1027,30 @@ static int qm_diff_regs_show(struct seq_file *s, void *unused) 
}

DEFINE_SHOW_ATTRIBUTE(qm_diff_regs);



static int qm_state_show(struct seq_file *s, void *unused)

{

	struct hisi_qm *qm = s->private;

	u32 val;

	int ret;



	/* If device is in suspended, directly return the idle state. */

	ret = hisi_qm_get_dfx_access(qm);

	if (!ret) {

		val = readl(qm->io_base + QM_IN_IDLE_ST_REG);

		hisi_qm_put_dfx_access(qm);

	} else if (ret == -EAGAIN) {

		val = QM_IN_IDLE_STATE;

	} else {

		return ret;

	}



	seq_printf(s, "%u\n", val);



	return 0;

}



DEFINE_SHOW_ATTRIBUTE(qm_state);



static ssize_t qm_status_read(struct file *filp, char __user *buffer,

			      size_t count, loff_t *pos)

{
@@ -1073,6 +1112,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(qm_atomic64_ops, qm_debugfs_atomic64_get, 
void hisi_qm_debug_init(struct hisi_qm *qm)

{

	struct dfx_diff_registers *qm_regs = qm->debug.qm_diff_regs;

	struct qm_dev_dfx *dev_dfx = &qm->debug.dev_dfx;

	struct qm_dfx *dfx = &qm->debug.dfx;

	struct dentry *qm_d;

	void *data;
@@ -1083,6 +1123,9 @@ void hisi_qm_debug_init(struct hisi_qm *qm) 


	/* only show this in PF */

	if (qm->fun_type == QM_HW_PF) {

		debugfs_create_file("qm_state", 0444, qm->debug.qm_d,

					qm, &qm_state_fops);



		qm_create_debugfs_file(qm, qm->debug.debug_root, CURRENT_QM);

		for (i = CURRENT_Q; i < DEBUG_FILE_NUM; i++)

			qm_create_debugfs_file(qm, qm->debug.qm_d, i);
@@ -1098,6 +1141,10 @@ void hisi_qm_debug_init(struct hisi_qm *qm) 


	debugfs_create_file("status", 0444, qm->debug.qm_d, qm,

			&qm_status_fops);



	debugfs_create_u32("dev_state", 0444, qm->debug.qm_d, &dev_dfx->dev_state);

	debugfs_create_u32("dev_timeout", 0644, qm->debug.qm_d, &dev_dfx->dev_timeout);



	for (i = 0; i < ARRAY_SIZE(qm_dfx_files); i++) {

		data = (atomic64_t *)((uintptr_t)dfx + qm_dfx_files[i].offset);

		debugfs_create_file(qm_dfx_files[i].name,

drivers/crypto/hisilicon/hpre/hpre_crypto.c

+23 −2
Original line number Diff line number Diff line
@@ -57,6 +57,9 @@ struct hpre_ctx; 
#define HPRE_DRV_ECDH_MASK_CAP		BIT(2)

#define HPRE_DRV_X25519_MASK_CAP	BIT(5)



static DEFINE_MUTEX(hpre_algs_lock);

static unsigned int hpre_available_devs;



typedef void (*hpre_cb)(struct hpre_ctx *ctx, void *sqe);



struct hpre_rsa_ctx {
@@ -2202,11 +2205,17 @@ static void hpre_unregister_x25519(struct hisi_qm *qm) 


int hpre_algs_register(struct hisi_qm *qm)

{

	int ret;

	int ret = 0;



	mutex_lock(&hpre_algs_lock);

	if (hpre_available_devs) {

		hpre_available_devs++;

		goto unlock;

	}



	ret = hpre_register_rsa(qm);

	if (ret)

		return ret;

		goto unlock;



	ret = hpre_register_dh(qm);

	if (ret)
@@ -2220,6 +2229,9 @@ int hpre_algs_register(struct hisi_qm *qm) 
	if (ret)

		goto unreg_ecdh;



	hpre_available_devs++;

	mutex_unlock(&hpre_algs_lock);



	return ret;



unreg_ecdh:
@@ -2228,13 +2240,22 @@ int hpre_algs_register(struct hisi_qm *qm) 
	hpre_unregister_dh(qm);

unreg_rsa:

	hpre_unregister_rsa(qm);

unlock:

	mutex_unlock(&hpre_algs_lock);

	return ret;

}



void hpre_algs_unregister(struct hisi_qm *qm)

{

	mutex_lock(&hpre_algs_lock);

	if (--hpre_available_devs)

		goto unlock;



	hpre_unregister_x25519(qm);

	hpre_unregister_ecdh(qm);

	hpre_unregister_dh(qm);

	hpre_unregister_rsa(qm);



unlock:

	mutex_unlock(&hpre_algs_lock);

}