Commit daa782a5 authored by Alim Akhtar's avatar Alim Akhtar Committed by Martin K. Petersen
Browse files

scsi: ufs: host: ufs-exynos: Add mphy apb clock mask 

Bit[3] of HCI_CLKSTOP_CTRL register is for enabling/disabling MPHY APB
clock. Lets add it to CLK_STOP_MASK, so that the same can be controlled
during clock masking/unmasking.

Link: https://lore.kernel.org/r/20220610104119.66401-6-alim.akhtar@samsung.com


Tested-by: default avatarChanho Park <chanho61.park@samsung.com>
Reviewed-by: default avatarChanho Park <chanho61.park@samsung.com>
Signed-off-by: default avatarAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent ea83df8e

drivers/ufs/host/ufs-exynos.c

+2 −1
Original line number Diff line number Diff line
@@ -52,11 +52,12 @@ 
#define HCI_ERR_EN_DME_LAYER	0x88

#define HCI_CLKSTOP_CTRL	0xB0

#define REFCLKOUT_STOP		BIT(4)

#define MPHY_APBCLK_STOP	BIT(3)

#define REFCLK_STOP		BIT(2)

#define UNIPRO_MCLK_STOP	BIT(1)

#define UNIPRO_PCLK_STOP	BIT(0)

#define CLK_STOP_MASK		(REFCLKOUT_STOP | REFCLK_STOP |\

				 UNIPRO_MCLK_STOP |\

				 UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\

				 UNIPRO_PCLK_STOP)

#define HCI_MISC		0xB4

#define REFCLK_CTRL_EN		BIT(7)