Commit da85e7ed authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mtd/for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux 

Pull MTD updates from Richard Weinberger:
 "MTD core changes:
   - Convert list_for_each to entry variant
   - Use MTD_DEVICE_ATTR_RO/RW() helper macros
   - Remove unnecessary OOM messages
   - Potential NULL dereference in mtd_otp_size()
   - Fix freeing of otp_info buffer
   - Create partname and partid debug files for child MTDs
   - tests:
      - Remove redundant assignment to err
      - Fix error return code in mtd_oobtest_init()
   - Add OTP NVMEM provider support
   - Allow specifying of_node
   - Convert sysfs sprintf/snprintf family to sysfs_emit

  Bindings changes:
   - Convert ti,am654-hbmc.txt to YAML schema
   - spi-nor: add otp property
   - Add OTP bindings
   - add YAML schema for the generic MTD bindings
   - Add brcm,trx-magic

  MTD device drivers changes:
   - Add support for microchip 48l640 EERAM
   - Remove superfluous "break"
   - sm_ftl:
      - Fix alignment of block comment
   - nftl:
      - Return -ENOMEM when kmalloc failed
   - nftlcore:
      - Remove set but rewrite variables
   - phram:
      - Fix error return code in phram_setup()
   - plat-ram:
      - Remove redundant dev_err call in platram_probe()

  MTD parsers changes:
   - Qcom:
      - Fix leaking of partition name
   - Redboot:
      - Fix style issues
      - Seek fis-index-block in the right node
   - trx:
      - Allow to use TRX parser on Mediatek SoCs
      - Allow to specify brcm, trx-magic in DT

  Raw NAND core:
   - Allow SDR timings to be nacked
   - Bring support for NV-DDR timings which involved a number of small
     preparation changes to bring new helpers, properly introduce NV-DDR
     structures, fill them, differenciate them and pick the best timing
     set.
   - Add the necessary infrastructure to parse the new gpio-cs property
     which aims at enlarging the number of available CS when a hardware
     controller is too constrained.
   - Update dead URL
   - Silence static checker warning in nand_setup_interface()
   - BBT:
      - Fix corner case in bad block table handling
   - onfi:
      - Use more recent ONFI specification wording
      - Use the BIT() macro when possible

  Raw NAND controller drivers:
   - Atmel:
      - Ensure the data interface is supported.
   - Arasan:
      - Finer grain NV-DDR configuration
      - Rename the data interface register
      - Use the right DMA mask
      - Leverage additional GPIO CS
      - Ensure proper configuration for the asserted target
      - Add support for the NV-DDR interface
      - Fix a macro parameter
   - brcmnand:
      - Convert bindings to json-schema
   - OMAP:
      - Various fixes and style improvements
      - Add larger page NAND chips support
   - PL35X:
      - New driver
   - QCOM:
      - Avoid writing to obsolete register
      - Delete an unneeded bool conversion
      - Allow override of partition parser
   - Marvell:
      - Minor documentation correction
      - Add missing clk_disable_unprepare() on error in
        marvell_nfc_resume()
   - R852:
      - Use DEVICE_ATTR_RO() helper macro
   - MTK:
      - Remove redundant dev_err call in mtk_ecc_probe()
   - HISI504:
      - Remove redundant dev_err call in probe

  SPI-NAND core:
   - Light reorganisation for the introduction of a core resume handler
   - Fix double counting of ECC stats

  SPI-NAND manufacturer drivers:
   - Macronix:
      - Add support for serial NAND flash

  SPI NOR core changes:
   - Ability to dump SFDP tables via sysfs
   - Support for erasing OTP regions on Winbond and similar flashes
   - Few API doc updates and fixes
   - Locking support for MX25L12805D

  SPI NOR controller drivers changes:
   - Use SPI_MODE_X_MASK in nxp-spifi
   - Intel Alder Lake-M SPI serial flash support"

* tag 'mtd/for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (125 commits)
  mtd: spi-nor: remove redundant continue statement
  mtd: rawnand: omap: Add larger page NAND chips support
  mtd: rawnand: omap: Various style fixes
  mtd: rawnand: omap: Check return values
  mtd: rawnand: omap: Rename a macro
  mtd: rawnand: omap: Aggregate the HW configuration of the ELM
  mtd: rawnand: pl353: Add support for the ARM PL353 SMC NAND controller
  dt-bindings: mtd: pl353-nand: Describe this hardware controller
  MAINTAINERS: Add PL353 NAND controller entry
  mtd: rawnand: qcom: avoid writing to obsolete register
  mtd: rawnand: marvell: Minor documentation correction
  mtd: rawnand: r852: use DEVICE_ATTR_RO() helper macro
  mtd: spinand: add SPI-NAND MTD resume handler
  mtd: spinand: Add spinand_init_flash() helper
  mtd: spinand: add spinand_read_cfg() helper
  mtd: rawnand: marvell: add missing clk_disable_unprepare() on error in marvell_nfc_resume()
  mtd: rawnand: arasan: Finer grain NV-DDR configuration
  mtd: rawnand: arasan: Rename the data interface register
  mtd: rawnand: onfi: Fix endianness when reading NV-DDR values
  mtd: rawnand: arasan: Use the right DMA mask
  ...
parents 8fc4fb17 0bcc3939

Documentation/ABI/testing/sysfs-bus-spi-devices-spi-nor

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What:		/sys/bus/spi/devices/.../spi-nor/jedec_id

Date:		April 2021

KernelVersion:	5.14

Contact:	linux-mtd@lists.infradead.org

Description:	(RO) The JEDEC ID of the SPI NOR flash as reported by the

		flash device.





What:		/sys/bus/spi/devices/.../spi-nor/manufacturer

Date:		April 2021

KernelVersion:	5.14

Contact:	linux-mtd@lists.infradead.org

Description:	(RO) Manufacturer of the SPI NOR flash.





What:		/sys/bus/spi/devices/.../spi-nor/partname

Date:		April 2021

KernelVersion:	5.14

Contact:	linux-mtd@lists.infradead.org

Description:	(RO) Part name of the SPI NOR flash.





What:		/sys/bus/spi/devices/.../spi-nor/sfdp

Date:		April 2021

KernelVersion:	5.14

Contact:	linux-mtd@lists.infradead.org

Description:	(RO) This attribute is only present if the SPI NOR flash

		device supports the "Read SFDP" command (5Ah).



		If present, it contains the complete SFDP (serial flash

		discoverable parameters) binary data of the flash.

Documentation/devicetree/bindings/memory-controllers/arm,pl353-smc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM PL353 Static Memory Controller (SMC) device-tree bindings



maintainers:

  - Miquel Raynal <miquel.raynal@bootlin.com>

  - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>



description:

  The PL353 Static Memory Controller is a bus where you can connect two kinds

  of memory interfaces, which are NAND and memory mapped interfaces (such as

  SRAM or NOR).



# We need a select here so we don't match all nodes with 'arm,primecell'

select:

  properties:

    compatible:

      contains:

        const: arm,pl353-smc-r2p1

  required:

    - compatible



properties:

  $nodename:

    pattern: "^memory-controller@[0-9a-f]+$"



  compatible:

    items:

      - const: arm,pl353-smc-r2p1

      - const: arm,primecell



  "#address-cells":

    const: 2



  "#size-cells":

    const: 1



  reg:

    items:

      - description:

          Configuration registers for the host and sub-controllers.

          The three chip select regions are defined in 'ranges'.



  clocks:

    items:

      - description: clock for the memory device bus

      - description: main clock of the SMC



  clock-names:

    items:

      - const: memclk

      - const: apb_pclk



  ranges:

    minItems: 1

    maxItems: 3

    description: |

      Memory bus areas for interacting with the devices. Reflects

      the memory layout with four integer values following:

      <cs-number> 0 <offset> <size>

    items:

      - description: NAND bank 0

      - description: NOR/SRAM bank 0

      - description: NOR/SRAM bank 1



  interrupts: true



patternProperties:

  "@[0-3],[a-f0-9]+$":

    type: object

    description: |

      The child device node represents the controller connected to the SMC

      bus. The controller can be a NAND controller or a pair of any memory

      mapped controllers such as NOR and SRAM controllers.



    properties:

      compatible:

        description:

          Compatible of memory controller.



      reg:

        items:

          - items:

              - description: |

                  Chip-select ID, as in the parent range property.

                minimum: 0

                maximum: 2

              - description: |

                  Offset of the memory region requested by the device.

              - description: |

                  Length of the memory region requested by the device.



    required:

      - compatible

      - reg



required:

  - compatible

  - reg

  - clock-names

  - clocks

  - "#address-cells"

  - "#size-cells"

  - ranges



additionalProperties: false



examples:

  - |

    smcc: memory-controller@e000e000 {

      compatible = "arm,pl353-smc-r2p1", "arm,primecell";

      reg = <0xe000e000 0x0001000>;

      clock-names = "memclk", "apb_pclk";

      clocks = <&clkc 11>, <&clkc 44>;

      ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */

                0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */

                0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */

      #address-cells = <2>;

      #size-cells = <1>;



      nfc0: nand-controller@0,0 {

        compatible = "arm,pl353-nand-r2p1";

        reg = <0 0 0x1000000>;

        #address-cells = <1>;

        #size-cells = <0>;

      };

    };

Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt

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Device tree bindings for ARM PL353 static memory controller



PL353 static memory controller supports two kinds of memory

interfaces.i.e NAND and SRAM/NOR interfaces.

The actual devices are instantiated from the child nodes of pl353 smc node.



Required properties:

- compatible		: Should be "arm,pl353-smc-r2p1", "arm,primecell".

- reg			: Controller registers map and length.

- clock-names		: List of input clock names - "memclk", "apb_pclk"

			  (See clock bindings for details).

- clocks		: Clock phandles (see clock bindings for details).

- address-cells		: Must be 2.

- size-cells		: Must be 1.



Child nodes:

 For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are

supported as child nodes.



for NAND partition information please refer the below file

Documentation/devicetree/bindings/mtd/partition.txt



Example:

	smcc: memory-controller@e000e000

			compatible = "arm,pl353-smc-r2p1", "arm,primecell";

			clock-names = "memclk", "apb_pclk";

			clocks = <&clkc 11>, <&clkc 44>;

			reg = <0xe000e000 0x1000>;

			#address-cells = <2>;

			#size-cells = <1>;

			ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region

				  0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region

				  0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region

			nand_0: flash@e1000000 {

				compatible = "arm,pl353-nand-r2p1"

				reg = <0 0 0x1000000>;

				(...)

			};

			nor0: flash@e2000000 {

				compatible = "cfi-flash";

				reg = <1 0 0x2000000>;

			};

			nor1: flash@e4000000 {

				compatible = "cfi-flash";

				reg = <2 0 0x2000000>;

			};

	};

Documentation/devicetree/bindings/mtd/arm,pl353-nand-r2p1.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/arm,pl353-nand-r2p1.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: PL353 NAND Controller device tree bindings



allOf:

  - $ref: "nand-controller.yaml"



maintainers:

  - Miquel Raynal <miquel.raynal@bootlin.com>

  - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>



properties:

  compatible:

    items:

      - const: arm,pl353-nand-r2p1



  reg:

    items:

      - items:

          - description: CS with regard to the parent ranges property

          - description: Offset of the memory region requested by the device

          - description: Length of the memory region requested by the device



required:

  - compatible

  - reg



unevaluatedProperties: false



examples:

  - |

    smcc: memory-controller@e000e000 {

      compatible = "arm,pl353-smc-r2p1", "arm,primecell";

      reg = <0xe000e000 0x0001000>;

      clock-names = "memclk", "apb_pclk";

      clocks = <&clkc 11>, <&clkc 44>;

      ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */

                0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */

                0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */

      #address-cells = <2>;

      #size-cells = <1>;



      nfc0: nand-controller@0,0 {

        compatible = "arm,pl353-nand-r2p1";

        reg = <0 0 0x1000000>;

        #address-cells = <1>;

        #size-cells = <0>;

      };

    };

Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt

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* Broadcom STB NAND Controller



The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND

flash chips. It has a memory-mapped register interface for both control

registers and for its data input/output buffer. On some SoCs, this controller is

paired with a custom DMA engine (inventively named "Flash DMA") which supports

basic PROGRAM and READ functions, among other features.



This controller was originally designed for STB SoCs (BCM7xxx) but is now

available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and

iProc/Cygnus. Its history includes several similar (but not fully register

compatible) versions.



Required properties:

- compatible       : May contain an SoC-specific compatibility string (see below)

                     to account for any SoC-specific hardware bits that may be

                     added on top of the base core controller.

                     In addition, must contain compatibility information about

                     the core NAND controller, of the following form:

                     "brcm,brcmnand" and an appropriate version compatibility

                     string, like "brcm,brcmnand-v7.0"

                     Possible values:

                         brcm,brcmnand-v2.1

                         brcm,brcmnand-v2.2

                         brcm,brcmnand-v4.0

                         brcm,brcmnand-v5.0

                         brcm,brcmnand-v6.0

                         brcm,brcmnand-v6.1

                         brcm,brcmnand-v6.2

                         brcm,brcmnand-v7.0

                         brcm,brcmnand-v7.1

                         brcm,brcmnand-v7.2

                         brcm,brcmnand-v7.3

                         brcm,brcmnand

- reg              : the register start and length for NAND register region.

                     (optional) Flash DMA register range (if present)

                     (optional) NAND flash cache range (if at non-standard offset)

- reg-names        : a list of the names corresponding to the previous register

                     ranges. Should contain "nand" and (optionally)

                     "flash-dma" or "flash-edu" and/or "nand-cache".

- interrupts       : The NAND CTLRDY interrupt, (if Flash DMA is available)

                     FLASH_DMA_DONE and if EDU is avaialble and used FLASH_EDU_DONE

- interrupt-names  : May be "nand_ctlrdy" or "flash_dma_done" or "flash_edu_done",

                     if broken out as individual interrupts.

                     May be "nand", if the SoC has the individual NAND

                     interrupts multiplexed behind another custom piece of

                     hardware

- #address-cells   : <1> - subnodes give the chip-select number

- #size-cells      : <0>



Optional properties:

- clock                     : reference to the clock for the NAND controller

- clock-names               : "nand" (required for the above clock)

- brcm,nand-has-wp          : Some versions of this IP include a write-protect

                              (WP) control bit. It is always available on >=

                              v7.0. Use this property to describe the rare

                              earlier versions of this core that include WP



 -- Additional SoC-specific NAND controller properties --



The NAND controller is integrated differently on the variety of SoCs on which it

is found. Part of this integration involves providing status and enable bits

with which to control the 8 exposed NAND interrupts, as well as hardware for

configuring the endianness of the data bus. On some SoCs, these features are

handled via standard, modular components (e.g., their interrupts look like a

normal IRQ chip), but on others, they are controlled in unique and interesting

ways, sometimes with registers that lump multiple NAND-related functions

together. The former case can be described simply by the standard interrupts

properties in the main controller node. But for the latter exceptional cases,

we define additional 'compatible' properties and associated register resources within the NAND controller node above.



 - compatible: Can be one of several SoC-specific strings. Each SoC may have

   different requirements for its additional properties, as described below each

   bullet point below.



   * "brcm,nand-bcm63138"

     - reg: (required) the 'NAND_INT_BASE' register range, with separate status

       and enable registers

     - reg-names: (required) "nand-int-base"



   * "brcm,nand-bcm6368"

     - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"

     - reg: (required) the 'NAND_INTR_BASE' register range, with combined status

       and enable registers, and boot address registers

     - reg-names: (required) "nand-int-base"



   * "brcm,nand-iproc"

     - reg: (required) the "IDM" register range, for interrupt enable and APB

       bus access endianness configuration, and the "EXT" register range,

       for interrupt status/ack.

     - reg-names: (required) a list of the names corresponding to the previous

       register ranges. Should contain "iproc-idm" and "iproc-ext".





* NAND chip-select



Each controller (compatible: "brcm,brcmnand") may contain one or more subnodes

to represent enabled chip-selects which (may) contain NAND flash chips. Their

properties are as follows.



Required properties:

- compatible                : should contain "brcm,nandcs"

- reg                       : a single integer representing the chip-select

                              number (e.g., 0, 1, 2, etc.)

- #address-cells            : see partition.txt

- #size-cells               : see partition.txt



Optional properties:

- nand-ecc-strength         : see nand-controller.yaml

- nand-ecc-step-size        : must be 512 or 1024. See nand-controller.yaml

- nand-on-flash-bbt         : boolean, to enable the on-flash BBT for this

                              chip-select. See nand-controller.yaml

- brcm,nand-oob-sector-size : integer, to denote the spare area sector size

                              expected for the ECC layout in use. This size, in

                              addition to the strength and step-size,

                              determines how the hardware BCH engine will lay

                              out the parity bytes it stores on the flash.

                              This property can be automatically determined by

                              the flash geometry (particularly the NAND page

                              and OOB size) in many cases, but when booting

                              from NAND, the boot controller has only a limited

                              number of available options for its default ECC

                              layout.



Each nandcs device node may optionally contain sub-nodes describing the flash

partition mapping. See partition.txt for more detail.





Example:



nand@f0442800 {

	compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";

	reg = <0xF0442800 0x600>,

	      <0xF0443000 0x100>;

	reg-names = "nand", "flash-dma";

	interrupt-parent = <&hif_intr2_intc>;

	interrupts = <24>, <4>;



	#address-cells = <1>;

	#size-cells = <0>;



	nandcs@1 {

		compatible = "brcm,nandcs";

		reg = <1>; // Chip select 1

		nand-on-flash-bbt;

		nand-ecc-strength = <12>;

		nand-ecc-step-size = <512>;



		// Partitions

		#address-cells = <1>;  // <2>, for 64-bit offset

		#size-cells = <1>;     // <2>, for 64-bit length

		flash0.rootfs@0 {

			reg = <0 0x10000000>;

		};

		flash0@0 {

			reg = <0 0>; // MTDPART_SIZ_FULL

		};

		flash0.kernel@10000000 {

			reg = <0x10000000 0x400000>;

		};

	};

};



nand@10000200 {

	compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",

		"brcm,brcmnand-v4.0", "brcm,brcmnand";

	reg = <0x10000200 0x180>,

	      <0x10000600 0x200>,

	      <0x100000b0 0x10>;

	reg-names = "nand", "nand-cache", "nand-int-base";

	interrupt-parent = <&periph_intc>;

	interrupts = <50>;

	clocks = <&periph_clk 20>;

	clock-names = "nand";



	#address-cells = <1>;

	#size-cells = <0>;



	nand0: nandcs@0 {

		compatible = "brcm,nandcs";

		reg = <0>;

		nand-on-flash-bbt;

		nand-ecc-strength = <1>;

		nand-ecc-step-size = <512>;

	};

};