Commit da0fcf7a authored Apr 19, 2022 by Marc Zyngier Committed by Kunkun Jiang May 16, 2023

KVM: arm64: Expose the WFXT feature to guests

mainline inclusion
from mainline-v5.19-rc1
commit 06e0b802
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I6YAMV
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=06e0b802583d7bbc075476d90da995ee3e6053d5



-------------------------------

Plumb in the capability, and expose WFxT to guests when available.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220419182755.601427-8-maz@kernel.org


Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>

parent 3eaf467a

arch/arm64/kernel/cpufeature.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -2270,6 +2270,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
		.min_field_value = 1,
		},
		#endif
		{
		.desc = "WFx with timeout",
		.capability = ARM64_HAS_WFXT,
		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
		.sys_reg = SYS_ID_AA64ISAR2_EL1,
		.sign = FTR_UNSIGNED,
		.field_pos = ID_AA64ISAR2_WFXT_SHIFT,
		.matches = has_cpuid_feature,
		.min_field_value = ID_AA64ISAR2_WFXT_SUPPORTED,
		},
		{},
		};

arch/arm64/kvm/sys_regs.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -1166,6 +1166,9 @@ static u64 read_id_reg(struct kvm_vcpu *vcpu,
		(0xfUL << ID_AA64ISAR1_API_SHIFT) \|
		(0xfUL << ID_AA64ISAR1_GPA_SHIFT) \|
		(0xfUL << ID_AA64ISAR1_GPI_SHIFT));
		} else if (id == SYS_ID_AA64ISAR2_EL1) {
		if (!cpus_have_final_cap(ARM64_HAS_WFXT))
		val &= ~(0xfUL << ID_AA64ISAR2_WFXT_SHIFT);
		} else if (id == SYS_ID_AA64DFR0_EL1) {
		/* Limit guests to PMUv3 for ARMv8.1 */
		val = cpuid_feature_cap_perfmon_field(val,