Commit d9e0f7a6 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dp: "inline" dp_ctrl_set_clock_rate("ctrl_link") 



"ctrl_link" is the clock from DP_CTRL_PM module. The result of setting
the rate for it would be a call to dev_pm_opp_set_rate(). Instead of
saving the rate inside struct dss_module_power, call the
devm_pm_opp_set_rate() directly.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/474712/
Link: https://lore.kernel.org/r/20220217055529.499829-3-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 1796c025

drivers/gpu/drm/msm/dp/dp_ctrl.c

+5 −2
Original line number Diff line number Diff line
@@ -1349,12 +1349,11 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) 
	opts_dp->lanes = ctrl->link->link_params.num_lanes;

	opts_dp->link_rate = ctrl->link->link_params.rate / 100;

	opts_dp->ssc = drm_dp_max_downspread(dpcd);

	dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link",

					ctrl->link->link_params.rate * 1000);



	phy_configure(phy, &dp_io->phy_opts);

	phy_power_on(phy);



	dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000);

	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);

	if (ret)

		DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
@@ -1462,6 +1461,7 @@ static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) 
	 * link clock might have been adjusted as part of the

	 * link maintenance.

	 */

	dev_pm_opp_set_rate(ctrl->dev, 0);

	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);

	if (ret) {

		DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
@@ -1493,6 +1493,7 @@ static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) 


	dp_catalog_ctrl_reset(ctrl->catalog);



	dev_pm_opp_set_rate(ctrl->dev, 0);

	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);

	if (ret) {

		DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
@@ -1929,6 +1930,7 @@ int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) 
		}

	}



	dev_pm_opp_set_rate(ctrl->dev, 0);

	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);

	if (ret) {

		DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
@@ -1997,6 +1999,7 @@ int dp_ctrl_off(struct dp_ctrl *dp_ctrl) 
	if (ret)

		DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret);



	dev_pm_opp_set_rate(ctrl->dev, 0);

	ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);

	if (ret) {

		DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);

drivers/gpu/drm/msm/dp/dp_power.c

+1 −32
Original line number Diff line number Diff line
@@ -151,44 +151,13 @@ static int dp_power_clk_deinit(struct dp_power_private *power) 
	return 0;

}



static int dp_power_clk_set_link_rate(struct dp_power_private *power,

			struct dss_clk *clk_arry, int num_clk, int enable)

{

	u32 rate;

	int i, rc = 0;



	for (i = 0; i < num_clk; i++) {

		if (clk_arry[i].clk) {

			if (clk_arry[i].type == DSS_CLK_PCLK) {

				if (enable)

					rate = clk_arry[i].rate;

				else

					rate = 0;



				rc = dev_pm_opp_set_rate(power->dev, rate);

				if (rc)

					break;

			}



		}

	}

	return rc;

}



static int dp_power_clk_set_rate(struct dp_power_private *power,

		enum dp_pm_type module, bool enable)

{

	int rc = 0;

	struct dss_module_power *mp = &power->parser->mp[module];



	if (module == DP_CTRL_PM) {

		rc = dp_power_clk_set_link_rate(power, mp->clk_config, mp->num_clk, enable);

		if (rc) {

			DRM_ERROR("failed to set link clks rate\n");

			return rc;

		}

	} else {



	if (module != DP_CTRL_PM) {

		if (enable) {

			rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);

			if (rc) {