Commit d9d95bca authored by Rasmus Villemoes's avatar Rasmus Villemoes Committed by Li Yang
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soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers 



Make it clear that these operate on big-endian registers (i.e. use the
iowrite*be primitives) before we introduce more uses of them and allow
the QE drivers to be built for platforms other than ppc32.

Reviewed-by: default avatarTimur Tabi <timur@kernel.org>
Signed-off-by: default avatarRasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: default avatarLi Yang <leoyang.li@nxp.com>
parent cf037a9b

drivers/net/wan/fsl_ucc_hdlc.c

+2 −2
Original line number Diff line number Diff line
@@ -623,7 +623,7 @@ static int ucc_hdlc_poll(struct napi_struct *napi, int budget) 


	if (howmany < budget) {

		napi_complete_done(napi, howmany);

		qe_setbits32(priv->uccf->p_uccm,

		qe_setbits_be32(priv->uccf->p_uccm,

				(UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);

	}

drivers/soc/fsl/qe/ucc.c

+5 −5
Original line number Diff line number Diff line
@@ -540,7 +540,7 @@ int ucc_set_tdm_rxtx_clk(u32 tdm_num, enum qe_clock clock, 
	cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l :

				  &qe_mux_reg->cmxsi1cr_h;



	qe_clrsetbits32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,

	qe_clrsetbits_be32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,

			   clock_bits << shift);



	return 0;
@@ -650,7 +650,7 @@ int ucc_set_tdm_rxtx_sync(u32 tdm_num, enum qe_clock clock, 


	shift = ucc_get_tdm_sync_shift(mode, tdm_num);



	qe_clrsetbits32(&qe_mux_reg->cmxsi1syr,

	qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr,

			   QE_CMXUCR_TX_CLK_SRC_MASK << shift,

			   source << shift);

include/soc/fsl/qe/qe.h

+9 −9
Original line number Diff line number Diff line
@@ -241,20 +241,20 @@ static inline int qe_alive_during_sleep(void) 
#define qe_muram_offset cpm_muram_offset

#define qe_muram_dma cpm_muram_dma



#define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))

#define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))

#define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))

#define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))



#define qe_setbits16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))

#define qe_clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))

#define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))

#define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))



#define qe_setbits8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))

#define qe_clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))

#define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))

#define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))



#define qe_clrsetbits32(addr, clear, set) \

#define qe_clrsetbits_be32(addr, clear, set) \

	iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))

#define qe_clrsetbits16(addr, clear, set) \

#define qe_clrsetbits_be16(addr, clear, set) \

	iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))

#define qe_clrsetbits8(addr, clear, set) \

#define qe_clrsetbits_8(addr, clear, set) \

	iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))



/* Structure that defines QE firmware binary files.