Loading arch/ia64/include/asm/pci.h +1 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,7 @@ extern unsigned long ia64_max_iommu_merge_mask; #define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL) #define HAVE_PCI_MMAP #define ARCH_GENERIC_PCI_MMAP_RESOURCE #define arch_can_pci_mmap_wc() 1 #define HAVE_PCI_LEGACY Loading arch/ia64/pci/pci.c +0 −30 Original line number Diff line number Diff line Loading @@ -418,36 +418,6 @@ pcibios_align_resource (void *data, const struct resource *res, return res->start; } int pci_mmap_page_range (struct pci_dev *dev, int bar, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine) { /* * I/O space cannot be accessed via normal processor loads and * stores on this platform. */ if (mmap_state == pci_mmap_io) /* * XXX we could relax this for I/O spaces for which ACPI * indicates that the space is 1-to-1 mapped. But at the * moment, we don't support multiple PCI address spaces and * the legacy I/O space is not 1-to-1 mapped, so this is moot. */ return -EINVAL; if (write_combine) vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); else vma->vm_page_prot = pgprot_device(vma->vm_page_prot); if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, vma->vm_end - vma->vm_start, vma->vm_page_prot)) return -EAGAIN; return 0; } /** * ia64_pci_get_legacy_mem - generic legacy mem routine * @bus: bus to get legacy memory base address for Loading Loading
arch/ia64/include/asm/pci.h +1 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,7 @@ extern unsigned long ia64_max_iommu_merge_mask; #define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL) #define HAVE_PCI_MMAP #define ARCH_GENERIC_PCI_MMAP_RESOURCE #define arch_can_pci_mmap_wc() 1 #define HAVE_PCI_LEGACY Loading
arch/ia64/pci/pci.c +0 −30 Original line number Diff line number Diff line Loading @@ -418,36 +418,6 @@ pcibios_align_resource (void *data, const struct resource *res, return res->start; } int pci_mmap_page_range (struct pci_dev *dev, int bar, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine) { /* * I/O space cannot be accessed via normal processor loads and * stores on this platform. */ if (mmap_state == pci_mmap_io) /* * XXX we could relax this for I/O spaces for which ACPI * indicates that the space is 1-to-1 mapped. But at the * moment, we don't support multiple PCI address spaces and * the legacy I/O space is not 1-to-1 mapped, so this is moot. */ return -EINVAL; if (write_combine) vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); else vma->vm_page_prot = pgprot_device(vma->vm_page_prot); if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, vma->vm_end - vma->vm_start, vma->vm_page_prot)) return -EAGAIN; return 0; } /** * ia64_pci_get_legacy_mem - generic legacy mem routine * @bus: bus to get legacy memory base address for Loading