Commit d9aa1da9 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2023-08-04' of... 

Merge tag 'drm-intel-gt-next-2023-08-04' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

Driver Changes:

- Avoid infinite GPU waits by avoidin premature release of request's
  reusable memory (Chris, Janusz)
- Expose RPS thresholds in sysfs (Tvrtko)
- Apply GuC SLPC min frequency softlimit correctly (Vinay)
- Restore SLPC efficient freq earlier (Vinay)
- Consider OA buffer boundary when zeroing out reports (Umesh)
- Extend Wa_14015795083 to TGL, RKL, DG1 and ADL (Matt R)
- Fix context workarounds with non-masked regs on MTL/DG2 (Lucas)
- Enable the CCS_FLUSH bit in the pipe control and in the CS for MTL+ (Andi)
- Update MTL workarounds 14018778641, 22016122933 (Tejas, Zhanjun)
- Ensure memory quiesced before AUX CCS invalidation (Jonathan)

- Add a gsc_info debugfs (Daniele)
- Invalidate the TLBs on each GT on multi-GT device (Chris)
- Fix a VMA UAF for multi-gt platform (Nirmoy)
- Do not use stolen on MTL due to HW bug (Nirmoy)
- Check HuC and GuC version compatibility on MTL (Daniele)
- Dump perf_limit_reasons for slow GuC init debug (Vinay)
- Replace kmap() with kmap_local_page() (Sumitra, Ira)
- Add sentinel to xehp_oa_b_counters for KASAN (Andrzej)
- Add the gen12_needs_ccs_aux_inv helper (Andi)
- Fixes and updates for GSC memory allocation (Daniele)
- Fix one wrong caching mode enum usage (Tvrtko)
- Fixes for GSC wakeref (Alan)

- Static checker fixes (Harshit, Arnd, Dan, Cristophe, David, Andi)
- Rename flags with bit_group_X according to the datasheet (Andi)
- Use direct alias for i915 in requests (Andrzej)
- Replace i915->gt0 with to_gt(i915) (Andi)
- Use the i915_vma_flush_writes helper (Tvrtko)
- Selftest improvements (Alan)
- Remove dead code (Tvrtko)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

# Conflicts:
#	drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZMy6kDd9npweR4uy@jlahtine-mobl.ger.corp.intel.com
parents 7c9aa0f7 28e67111

drivers/gpu/drm/i915/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -132,6 +132,7 @@ gt-y += \ 
	gt/intel_sseu.o \

	gt/intel_sseu_debugfs.o \

	gt/intel_timeline.o \

	gt/intel_tlb.o \

	gt/intel_wopcm.o \

	gt/intel_workarounds.o \

	gt/shmem_utils.o \
@@ -197,6 +198,7 @@ i915-y += \ 
	  gt/uc/intel_gsc_fw.o \

	  gt/uc/intel_gsc_proxy.o \

	  gt/uc/intel_gsc_uc.o \

	  gt/uc/intel_gsc_uc_debugfs.o \

	  gt/uc/intel_gsc_uc_heci_cmd_submit.o \

	  gt/uc/intel_guc.o \

	  gt/uc/intel_guc_ads.o \

drivers/gpu/drm/i915/gem/i915_gem_domain.c

+2 −4
Original line number Diff line number Diff line
@@ -68,10 +68,8 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) 
	switch (obj->write_domain) {

	case I915_GEM_DOMAIN_GTT:

		spin_lock(&obj->vma.lock);

		for_each_ggtt_vma(vma, obj) {

			if (i915_vma_unset_ggtt_write(vma))

				intel_gt_flush_ggtt_writes(vma->vm->gt);

		}

		for_each_ggtt_vma(vma, obj)

			i915_vma_flush_writes(vma);

		spin_unlock(&obj->vma.lock);



		i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

+21 −4
Original line number Diff line number Diff line
@@ -2229,8 +2229,8 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq) 
	u32 *cs;

	int i;



	if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {

		drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");

	if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {

		drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n");

		return -EINVAL;

	}
@@ -2691,6 +2691,7 @@ static int 
eb_select_engine(struct i915_execbuffer *eb)

{

	struct intel_context *ce, *child;

	struct intel_gt *gt;

	unsigned int idx;

	int err;
@@ -2714,10 +2715,17 @@ eb_select_engine(struct i915_execbuffer *eb) 
		}

	}

	eb->num_batches = ce->parallel.number_children + 1;

	gt = ce->engine->gt;



	for_each_child(ce, child)

		intel_context_get(child);

	intel_gt_pm_get(ce->engine->gt);

	intel_gt_pm_get(gt);

	/*

	 * Keep GT0 active on MTL so that i915_vma_parked() doesn't

	 * free VMAs while execbuf ioctl is validating VMAs.

	 */

	if (gt->info.id)

		intel_gt_pm_get(to_gt(gt->i915));



	if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {

		err = intel_context_alloc_state(ce);
@@ -2756,7 +2764,10 @@ eb_select_engine(struct i915_execbuffer *eb) 
	return err;



err:

	intel_gt_pm_put(ce->engine->gt);

	if (gt->info.id)

		intel_gt_pm_put(to_gt(gt->i915));



	intel_gt_pm_put(gt);

	for_each_child(ce, child)

		intel_context_put(child);

	intel_context_put(ce);
@@ -2769,6 +2780,12 @@ eb_put_engine(struct i915_execbuffer *eb) 
	struct intel_context *child;



	i915_vm_put(eb->context->vm);

	/*

	 * This works in conjunction with eb_select_engine() to prevent

	 * i915_vma_parked() from interfering while execbuf validates vmas.

	 */

	if (eb->gt->info.id)

		intel_gt_pm_put(to_gt(eb->gt->i915));

	intel_gt_pm_put(eb->gt);

	for_each_child(eb->context, child)

		intel_context_put(child);

drivers/gpu/drm/i915/gem/i915_gem_object_types.h

+3 −1
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ 
#include "i915_selftest.h"

#include "i915_vma_resource.h"



#include "gt/intel_gt_defines.h"



struct drm_i915_gem_object;

struct intel_fronbuffer;

struct intel_memory_region;
@@ -675,7 +677,7 @@ struct drm_i915_gem_object { 
		 */

		bool dirty:1;



		u32 tlb;

		u32 tlb[I915_MAX_GT];

	} mm;



	struct {

drivers/gpu/drm/i915/gem/i915_gem_pages.c

+9 −6
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 
#include <drm/drm_cache.h>



#include "gt/intel_gt.h"

#include "gt/intel_gt_pm.h"

#include "gt/intel_tlb.h"



#include "i915_drv.h"

#include "i915_gem_object.h"
@@ -193,13 +193,16 @@ static void unmap_object(struct drm_i915_gem_object *obj, void *ptr) 
static void flush_tlb_invalidate(struct drm_i915_gem_object *obj)

{

	struct drm_i915_private *i915 = to_i915(obj->base.dev);

	struct intel_gt *gt = to_gt(i915);

	struct intel_gt *gt;

	int id;



	if (!obj->mm.tlb)

	for_each_gt(gt, i915, id) {

		if (!obj->mm.tlb[id])

			return;



	intel_gt_invalidate_tlb(gt, obj->mm.tlb);

	obj->mm.tlb = 0;

		intel_gt_invalidate_tlb_full(gt, obj->mm.tlb[id]);

		obj->mm.tlb[id] = 0;

	}

}



struct sg_table *