Commit d9943b6d authored by Chun-Jie Chen's avatar Chun-Jie Chen Committed by Stephen Boyd
Browse files

clk: mediatek: Add MT8195 ipesys clock support 



Add MT8195 ipesys clock controller which provides clock gate
control for Image Process Engine.

Signed-off-by: default avatarChun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-14-chun-jie.chen@mediatek.com


Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 9c4fec14

drivers/clk/mediatek/Makefile

+2 −1
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@@ -82,6 +82,7 @@ obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o 
obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o

obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o \

				   clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o \

				   clk-mt8195-cam.o clk-mt8195-ccu.o clk-mt8195-img.o

				   clk-mt8195-cam.o clk-mt8195-ccu.o clk-mt8195-img.o \

				   clk-mt8195-ipe.o

obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o

obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o

drivers/clk/mediatek/clk-mt8195-ipe.c

0 → 100644
+51 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

//

// Copyright (c) 2021 MediaTek Inc.

// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>



#include "clk-gate.h"

#include "clk-mtk.h"



#include <dt-bindings/clock/mt8195-clk.h>

#include <linux/clk-provider.h>

#include <linux/platform_device.h>



static const struct mtk_gate_regs ipe_cg_regs = {

	.set_ofs = 0x0,

	.clr_ofs = 0x0,

	.sta_ofs = 0x0,

};



#define GATE_IPE(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)



static const struct mtk_gate ipe_clks[] = {

	GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 0),

	GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "top_ipe", 1),

	GATE_IPE(CLK_IPE_ME, "ipe_me", "top_ipe", 2),

	GATE_IPE(CLK_IPE_TOP, "ipe_top", "top_ipe", 3),

	GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "top_ipe", 4),

};



static const struct mtk_clk_desc ipe_desc = {

	.clks = ipe_clks,

	.num_clks = ARRAY_SIZE(ipe_clks),

};



static const struct of_device_id of_match_clk_mt8195_ipe[] = {

	{

		.compatible = "mediatek,mt8195-ipesys",

		.data = &ipe_desc,

	}, {

		/* sentinel */

	}

};



static struct platform_driver clk_mt8195_ipe_drv = {

	.probe = mtk_clk_simple_probe,

	.driver = {

		.name = "clk-mt8195-ipe",

		.of_match_table = of_match_clk_mt8195_ipe,

	},

};

builtin_platform_driver(clk_mt8195_ipe_drv);