Commit d97fd7a0 authored by Jun Lei's avatar Jun Lei Committed by Alex Deucher
Browse files

drm/amd/display: enable dchub request limit for DCN 3.2.x 



[why]
HW recommend we enable this for better DF QoS for DCN 3.2.x

[how]
Add interfaces to hubbub to program register
Add initialization as part of init_hw
Add default settings for DCN 3.2.x
Add registry override for debug/tuning

Reviewed-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarJun Lei <jun.lei@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2ec3a0f0

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -408,6 +408,7 @@ struct dc_config { 
	bool use_default_clock_table;

	bool force_bios_enable_lttpr;

	uint8_t force_bios_fixed_vs;

	int sdpif_request_limit_words_per_umc;



};

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h

+3 −1
Original line number Diff line number Diff line
@@ -171,6 +171,7 @@ struct dcn_hubbub_registers { 
	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;

	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;

	uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D;

	uint32_t SDPIF_REQUEST_RATE_LIMIT;

};



#define HUBBUB_REG_FIELD_LIST_DCN32(type) \
@@ -360,7 +361,8 @@ struct dcn_hubbub_registers { 
		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;\

		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;\

		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;\

		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D

		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;\

		type SDPIF_REQUEST_RATE_LIMIT





struct dcn_hubbub_shift {

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c

+18 −0
Original line number Diff line number Diff line
@@ -72,6 +72,23 @@ static void dcn32_init_crb(struct hubbub *hubbub) 
	REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x47F);

}



void hubbub32_set_request_limit(struct hubbub *hubbub, int memory_channel_count, int words_per_channel)

{

	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);



	uint32_t request_limit = 3 * memory_channel_count * words_per_channel / 4;



	ASSERT((request_limit & (~0xFFF)) == 0); //field is only 24 bits long

	ASSERT(request_limit > 0); //field is only 24 bits long



	if (request_limit > 0xFFF)

		request_limit = 0xFFF;



	if (request_limit > 0)

		REG_UPDATE(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, request_limit);

}





void dcn32_program_det_size(struct hubbub *hubbub, int hubp_inst, unsigned int det_buffer_size_in_kbyte)

{

	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
@@ -949,6 +966,7 @@ static const struct hubbub_funcs hubbub32_funcs = { 
	.init_crb = dcn32_init_crb,

	.hubbub_read_state = hubbub2_read_state,

	.force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,

	.set_request_limit = hubbub32_set_request_limit

};



void hubbub32_construct(struct dcn20_hubbub *hubbub2,

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h

+6 −2
Original line number Diff line number Diff line
@@ -82,7 +82,8 @@ 
	SR(DCN_VM_FAULT_ADDR_MSB),\

	SR(DCN_VM_FAULT_ADDR_LSB),\

	SR(DCN_VM_FAULT_CNTL),\

	SR(DCN_VM_FAULT_STATUS)

	SR(DCN_VM_FAULT_STATUS),\

	SR(SDPIF_REQUEST_RATE_LIMIT)



#define HUBBUB_MASK_SH_LIST_DCN32(mask_sh)\

	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
@@ -159,7 +160,8 @@ 
	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \

	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \

	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \

	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh)

	HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh),\

	HUBBUB_SF(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, mask_sh)



bool hubbub32_program_urgent_watermarks(

		struct hubbub *hubbub,
@@ -200,4 +202,6 @@ void hubbub32_construct(struct dcn20_hubbub *hubbub2, 
	int pixel_chunk_size_kb,

	int config_return_buffer_size_kb);



void hubbub32_set_request_limit(struct hubbub *hubbub, int umc_count, int words_per_umc);



#endif

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

+3 −0
Original line number Diff line number Diff line
@@ -984,6 +984,9 @@ void dcn32_init_hw(struct dc *dc) 
	if (dc->res_pool->hubbub->funcs->init_crb)

		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);



	if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)

		dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);



	// Get DMCUB capabilities

	if (dc->ctx->dmub_srv) {

		dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);