Unverified Commit d96c2ce0 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!13920 RDMA/bnxt_re: Fix a bug while setting up Level-2 PBL pages 

Merge Pull Request from: @ci-robot 
 
PR sync from: Wang Liang <wangliang74@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/MSQ4K4A4E3EP5DZCW3UNQUSFGXE6GRFE/ 
 
https://gitee.com/src-openeuler/kernel/issues/IB2YUP 
 
Link:https://gitee.com/openeuler/kernel/pulls/13920

 

Reviewed-by: default avatarZhang Changzhong <zhangchangzhong@huawei.com>
Reviewed-by: default avatarLi Nan <linan122@huawei.com>
Signed-off-by: default avatarLi Nan <linan122@huawei.com>
parents 920d5152 92e07c26

drivers/infiniband/hw/bnxt_re/qplib_res.c

+3 −16
Original line number Diff line number Diff line
@@ -256,22 +256,9 @@ int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq, 
			dst_virt_ptr =

				(dma_addr_t **)hwq->pbl[PBL_LVL_0].pg_arr;

			src_phys_ptr = hwq->pbl[PBL_LVL_1].pg_map_arr;

			if (hwq_attr->type == HWQ_TYPE_MR) {

			/* For MR it is expected that we supply only 1 contigous

			 * page i.e only 1 entry in the PDL that will contain

			 * all the PBLs for the user supplied memory region

			 */

				for (i = 0; i < hwq->pbl[PBL_LVL_1].pg_count;

				     i++)

					dst_virt_ptr[0][i] = src_phys_ptr[i] |

						flag;

			} else {

				for (i = 0; i < hwq->pbl[PBL_LVL_1].pg_count;

				     i++)

					dst_virt_ptr[PTR_PG(i)][PTR_IDX(i)] =

						src_phys_ptr[i] |

						PTU_PDE_VALID;

			}

			for (i = 0; i < hwq->pbl[PBL_LVL_1].pg_count; i++)

				dst_virt_ptr[0][i] = src_phys_ptr[i] | flag;



			/* Alloc or init PTEs */

			rc = __alloc_pbl(res, &hwq->pbl[PBL_LVL_2],

					 hwq_attr->sginfo);